Abstract: A computer having a processing unit with improved performance characteristics. The computer includes a floating point multiplier, a floating point arithmetic logic unit (ALU), a first clock generator for generating a first clock and a second clock generator for generating a second clock. The second clock is generated to have a fixed relationship with the first clock. Specifically, the first clock is delayed and inverted to produce the second clock. The multiplier includes an output port operating under control of the second clock and coupled to provide data to a first input port of the adder. The adder includes both the first input port and a second input port, both operating under control of the second clock. A first and second input port of the multiplier and an output port of the adder operate under control of the first clock. The described configuration allows operation with reduced latency.

Abstract: A circuit for preserving sign information in a computer system. The computer system is capable of comparing and operating on the absolute value of two operands utilizing a pipelined architecture. Sign information is preserved through the use of a first plurality of stages corresponding to stages of the pipeline for storing sign information of a first operand and a second plurality of stages corresponding to stages of the pipeline for storing sign information of a second operand. Sign information is piped through the first and second plurality of stages under common control with the control for the pipeline. Upon completion of the comparison operation, the sign information for the operands is available. Further, the sign information for the first and second operands are coupled as inputs to a multiplexor.