Abstract: A system and method for repeat field detection for use in rate conversion and video encoding of the type contemplated by the MPEG standards. Before encoding a frame, first field in the current frame is compared to the previously occurring field of the same parity. Next, a single number (the inter-field parameter) is generated, which is a measure of the difference between the two fields. If the inter-field parameter is below a threshold a signal is generated to indicate that the current field is a repeat of the previous field of the same parity. Otherwise, the signal is generated to indicate that the field is not a repeat of the previous field of the same parity (i.e. the field likely contains at least one small area of motion).

Abstract: A method for encoding bitstream headers in a processor where templates for the bitstream header are stored in a processor buffer. The templates are addressable by programmable instructions, and the processor has a status register containing a bit for each header type. The status register is modifiable during the encoding process with a data pattern indicating the headers needed for encoding with the bitstream. In this way when a bit is set to 1 the predefined header type is generated and shipped to the bitstream. The header is generated by processing the header buffer template entries associated with the header type.

Abstract: A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.

Abstract: A mechanism translates a particular macroinstruction into its associated microprogram routine in a general purpose microprogrammed computer. The macroinstruction is capable of execution by either hardware or by microprogram. A table-look up approach is employed for a microprogrammed macroinstruction. The table is embedded in random-access-memory and contains entries representing the origins of various microprogram routines to execute the macroinstruction. The table entries are addressed by bits generated from the operation-code of the macroinstruction. The output of the table is used to address a single level control store containing the microprogram routines. Hardware is assembled in a single facility that is accessible by the microprogram routines to minimize the size of the microprogram routines required to execute the macroinstruction.

Abstract: Apparatus for improving the efficiency of computer instructions which transfer data from memory to machine registers and from machine registers to memory. The difficulty arises because such instructions may require data transfers of a variable number of bytes, may involve transfer across word boundaries within memory, and may use a number of machine registers. These features are important to programs which process variable amounts of data at different storage locations. Such transfer operations are performed by "mini-instructions", which are a proper subset of instructions that already exist within the current repertoire. However, the "mini-instructions" used are limited in the use of variables to only those which make most effective use of the hardware architecture. One or more "mini-instructions" must be used to execute the actual software instruction. Because the mini-instructions needed are a proper subset of the actual software instruction, little additional hardware is required.

Abstract: A sequence controller of an instruction processing unit (IPU) in a data processing system places the IPU is either a ready, go, hold-on-old, hold-on-new, or cancel state. If the IPU is ready to execute another instruction, the sequence controller places the IPU in the ready state. When an instruction is received for execution, and execution commences, the sequence controller places the IPU in the GO state. If at least one or more operands associated with the execution of an instruction are not ready when execution is scheduled to commence, the sequence controller places the IPU in a hold-on-new state, holding the pendency of the execution of the particular instruction, until the operands are available.

Abstract: Apparatus and method which provides a variable instruction stack. Instructions to be executed are fed into a single input multiple output stack register feeding from the lowest to the highest level. Instructions are provided with a valid bit to distinguish instructions requiring execution from those requiring no execution (NOOP). When an instruction not requiring execution (NOOP) propagates to the highest level, the execution unit receives an instruction in a lower level of the stack avoiding any idle time of the execution unit waiting for an executable instruction to propagate to the highest level.

Abstract: An apparatus and method are disclosed for implementing the system architectural requirement of precise interrupt reporting in a pipelined processor with multiple functional units. Since the expense of an interrupt pipeline is warranted only for those interrupts that occur frequently--specifically, those arising from virtual memory management--the apparatus utilizes an interrupt pipeline for frequently occurring interrupts, and a slower, but much less costly, software-based system for precisely reporting the remaining interrupts. The software-based system is facilitated by an instruction numbering and tracing scheme, whereby pertinent information concerning executed instructions is recorded as the instructions pass through the processor pipeline and potentially to other functional units. A software interrupt handler may use this information to isolate and precisely report an interrupt.

Abstract: An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B)>0, or a second branch condition ((Q+R)-B).ltoreq.0.