Patents by Inventor Agostino Pirovano

Agostino Pirovano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11895851
    Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Lorenzo Fratin
  • Patent number: 11869585
    Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Agostino Pirovano, Innocenzo Tortorelli
  • Publication number: 20230395113
    Abstract: Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 7, 2023
    Inventors: Giorgio Servalli, Marcello Mariani, Agostino Pirovano
  • Patent number: 11817148
    Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11798620
    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 11769551
    Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11763886
    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
  • Patent number: 11765912
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • Patent number: 11735261
    Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli, Fabio Pellizzer
  • Publication number: 20230260581
    Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Agostino Pirovano, Fabio Pellizzer, Innocenzo Tortorelli
  • Publication number: 20230262995
    Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11721394
    Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11696454
    Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
  • Patent number: 11647638
    Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Anna Maria Conti, Fabio Pellizzer, Agostino Pirovano, Kolya Yastrebenetsky
  • Publication number: 20230114077
    Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Agostino Pirovano, Lorenzo Fratin
  • Patent number: 11587979
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • Patent number: 11574957
    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
  • Publication number: 20230027799
    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
    Type: Application
    Filed: August 4, 2022
    Publication date: January 26, 2023
    Inventors: Stephen W. Russell, Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer, Lorenzo Fratin
  • Publication number: 20230005535
    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 5, 2023
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
  • Patent number: 11545625
    Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Kolya Yastrebenetsky, Fabio Pellizzer