Patents by Inventor Agrawal Aditya Binodkumar

Agrawal Aditya Binodkumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Robust method for integration of bump cells in semiconductor device design
    Patent number: 8239802
    Abstract: A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Yi Liu, Chung-Hsing Wang, Agrawal Aditya Binodkumar
  • ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN
    Publication number: 20110083115
    Abstract: A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Yi LIU, Chung-Hsing WANG, Agrawal Aditya BINODKUMAR