Abstract: Method and system that test device sensitivity according to whether the device passes or fails when subjected to a test signal. The device may be repeatedly subjected to test signal at varying operating parameters in order to assess pass-fail threshold at which the device transitions from operating properly/improperly to operating improperly/properly.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.

Abstract: Method and system that test device sensitivity according to whether the device passes or fails when subjected to a test signal. The device may be repeatedly subjected to test signal at varying operating parameters in order to assess pass-fail threshold at which the device transitions from operating properly/improperly to operating improperly/properly.