Patents by Inventor Agustinus Sutandi
Agustinus Sutandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9360926Abstract: Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.Type: GrantFiled: August 1, 2014Date of Patent: June 7, 2016Assignee: Synopsys, Inc.Inventors: Yanyi Liu Wong, Vikramaditya Kundur, Agustinus Sutandi, Ross Peterson, Rebecca Shiu Yun Cheng, Troy Gilliland, Martin Niset
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Publication number: 20160034015Abstract: Methods and systems for storing data are disclosed. The systems are configured to perform the methods and the methods may include, for example, receiving electronic data to be stored, partitioning the data into multiple segments, and storing each segment in a memory during a separate write cycle. The methods may also include programming a compensation load so that power provided by a power supply during the storing of each segment is substantially the same.Type: ApplicationFiled: August 1, 2014Publication date: February 4, 2016Inventors: Yanyi Liu Wong, Vikramaditya Kundur, Agustinus Sutandi, Ross Peterson, Rebecca Shiu Yun Cheng, Troy Gilliland, Martin Niset
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Patent number: 9230674Abstract: A memory system with improved power consumption and operation speed. A memory system performs a data read operation in a low power read mode to improve operation speed and reduce power consumption by biasing bit cells in the memory system at a negative voltage. The use of the negative voltage minimizes changing of voltages of the bit cells. Additionally, the memory system performs data read operation in a margin read mode to improve accuracy of the reading by biasing the bit cells at a positive voltage.Type: GrantFiled: October 22, 2014Date of Patent: January 5, 2016Assignee: Synopsys, Inc.Inventors: Yanyi Liu Wong, Agustinus Sutandi
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Patent number: 8937464Abstract: Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node.Type: GrantFiled: July 15, 2011Date of Patent: January 20, 2015Assignee: Synopsys Inc.Inventors: Yanyi L. Wong, Agustinus Sutandi
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Patent number: 8749297Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.Type: GrantFiled: February 15, 2013Date of Patent: June 10, 2014Assignee: Synopsys, Inc.Inventors: Agustinus Sutandi, Yanyi L. Wong
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Patent number: 8729883Abstract: A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.Type: GrantFiled: June 29, 2011Date of Patent: May 20, 2014Assignee: Synopsys, Inc.Inventors: Yanyi L. Wong, Agustinus Sutandi
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Patent number: 8400208Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.Type: GrantFiled: December 14, 2011Date of Patent: March 19, 2013Assignee: Synopsys, Inc.Inventors: Agustinus Sutandi, Yanyi L. Wong
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Publication number: 20130015831Abstract: Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: SYNOPSYS INC.Inventors: Yanyi L. WONG, Agustinus Sutandi
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Publication number: 20130002228Abstract: A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: SYNOPSYS INC.Inventors: Yanyi L. WONG, Agustinus Sutandi
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Publication number: 20120086498Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.Type: ApplicationFiled: December 14, 2011Publication date: April 12, 2012Applicant: SYNOPSYS, INC.Inventors: Agustinus Sutandi, Yanyi L. Wong
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Patent number: 8098088Abstract: Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.Type: GrantFiled: June 20, 2008Date of Patent: January 17, 2012Assignee: Synopsys, Inc.Inventors: Agustinus Sutandi, Yanyi L. Wong
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Patent number: 7724571Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.Type: GrantFiled: October 31, 2007Date of Patent: May 25, 2010Assignee: Virage Logic CorporationInventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
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Patent number: 7724570Abstract: Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.Type: GrantFiled: October 31, 2007Date of Patent: May 25, 2010Assignee: Virage Logic CorporationInventors: Chad A. Lindhorst, Todd E. Humes, Alex May, Agustinus Sutandi
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Patent number: 6812751Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.Type: GrantFiled: October 15, 2002Date of Patent: November 2, 2004Assignee: HPL Technologies, Inc.Inventors: Agustinus Sutandi, Daran DeShazo, Jason Stevens, Craig Waller
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Patent number: 6741500Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.Type: GrantFiled: October 4, 2002Date of Patent: May 25, 2004Assignee: HPL Technologies, Inc.Inventors: Daran DeShazo, Agustinus Sutandi, Jason Stevens
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Publication number: 20040070429Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.Type: ApplicationFiled: October 15, 2002Publication date: April 15, 2004Inventors: Agustinus Sutandi, Daran DeShazo, Jason Stevens, Craig Waller
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Publication number: 20040066670Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.Type: ApplicationFiled: October 4, 2002Publication date: April 8, 2004Inventors: Daran DeShazo, Agustinus Sutandi, Jason Stevens