Patents by Inventor Ah Chan Kim
Ah Chan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11789515Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: GrantFiled: April 28, 2022Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
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Patent number: 11747853Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: GrantFiled: April 5, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
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Publication number: 20220261061Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: ApplicationFiled: April 28, 2022Publication date: August 18, 2022Inventors: JAE GON LEE, AH CHAN KIM, JIN OOK SONG, JAE YOUNG LEE, YOUN SIK CHOI
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Publication number: 20220229464Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: ApplicationFiled: April 5, 2022Publication date: July 21, 2022Inventors: HO YEON JEON, AH CHAN KIM, JAE GON LEE
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Patent number: 11340685Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: GrantFiled: January 27, 2021Date of Patent: May 24, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
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Patent number: 11314278Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: GrantFiled: January 21, 2021Date of Patent: April 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
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Publication number: 20210247834Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: ApplicationFiled: January 27, 2021Publication date: August 12, 2021Inventors: JAE GON LEE, AH CHAN KIM, JIN OOK SONG, JAE YOUNG LEE, YOUN SIK CHOI
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Publication number: 20210141412Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: ApplicationFiled: January 21, 2021Publication date: May 13, 2021Inventors: HO YEON JEON, Ah Chan Kim, Jae Gon Lee
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Patent number: 10969854Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: GrantFiled: May 20, 2019Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
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Patent number: 10928849Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: GrantFiled: April 24, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
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Patent number: 10503674Abstract: A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.Type: GrantFiled: February 3, 2017Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
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Patent number: 10475501Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.Type: GrantFiled: April 6, 2018Date of Patent: November 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Yeon Jeon, Ah Chan Kim, Min Joung Lee, Youn-Sik Choi
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Publication number: 20190278357Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: ApplicationFiled: May 20, 2019Publication date: September 12, 2019Inventors: JAE GON LEE, AH CHAN KIM, JIN OOK SONG, JAE YOUNG LEE, YOUN SIK CHOI
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Publication number: 20190250659Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: HO YEON JEON, AH CHAN KIM, JAE GON LEE
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Patent number: 10303203Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.Type: GrantFiled: January 25, 2017Date of Patent: May 28, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
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Patent number: 10296065Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.Type: GrantFiled: January 25, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
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Patent number: 10296066Abstract: A system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode.Type: GrantFiled: January 25, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ah Chan Kim, Jae Gon Lee, Min Joung Lee
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Patent number: 10248155Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.Type: GrantFiled: January 25, 2017Date of Patent: April 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se Hun Kim, Ah Chan Kim, Youn Sik Choi, Jae Gon Lee
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Publication number: 20190057733Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.Type: ApplicationFiled: April 6, 2018Publication date: February 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ho-Yeon JEON, Ah Chan KIM, Min Joung LEE, Youn-Sik CHOI
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Publication number: 20170220495Abstract: A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.Type: ApplicationFiled: February 3, 2017Publication date: August 3, 2017Inventors: HO YEON JEON, AH CHAN KIM, JAE GON LEE