Patents by Inventor Ah Lek Hu

Ah Lek Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7181835
    Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: February 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
  • Patent number: 7023074
    Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Jaime A. Bayan, Santhiran Nadarajah, Ah Lek Hu
  • Patent number: 6872599
    Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 29, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Felix C. Li, Jaime A. Bayan, Santhiran Nadarajah, Ah Lek Hu
  • Publication number: 20040143962
    Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 29, 2004
    Applicant: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
  • Patent number: 6698088
    Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: March 2, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
  • Patent number: 6686652
    Abstract: An assembly and method suitable for use in packaging integrated circuits including a support substrate for supporting an integrated circuit die embedded in a molded encapsulating cap. The substrate includes a conductive die attach pad adapted to be molded into the encapsulating cap. The pad includes an interior facing support surface and a spaced-apart exterior facing exposed surface defined by a peripheral edge. The support surface is adapted to support the embedded die, while the exposed surface is to be exposed from the encapsulating cap. The attach pad further includes a locking ledge portion extending outward peripherally beyond at least a portion of the exposed surface peripheral edge. This ledge is adapted to be subtended in the encapsulating cap in a manner substantially preventing a pull-out of the attach pad in a direction away from the encapsulating cap.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: February 3, 2004
    Assignee: National Semiconductor
    Inventors: Jaime Bayan, Peter H. Spalding, Harry Cheng-Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
  • Patent number: 6629880
    Abstract: A system comprising a rotary buffing device for removing the mold-flash from leadless leadframe substrate panels is described. The leadless leadframe substrate panels have bottom surfaces that contain electrical contact landing and die attach pad surfaces. Covering at least some of the surfaces of the electrical contact landings and the die attach pads are formations of mold-flash, which are thin layers of molding material. The rotary buffing device is rotated at a sufficiently high rate such that the formations of flash are brushed (or buffed) off the bottom surfaces as the rotary wheel is run along the substrate panels.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: October 7, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Aik Seng Kang, Ah Lek Hu, Harry Kam Cheng Hong
  • Patent number: 6467278
    Abstract: A cooling system to reduce damage resulting from panel singulation is provided. A panel may be formed by encapsulating a lead frame with mounted dice. The encapsulating material may be a composite, plastic, or ceramic. Singulation may be a cutting done by laser, water jet, or saw. A chiller system cools a fluid, such as water, to a temperature below 16° C. The cooled fluid is dispensed to a part of the panel being singulated. For example, if a circular saw is used to cut the panel, a plurality of nozzles may be used to direct the fluid to the part of the saw cutting the panel, which defines the part of the panel being singulated. The cooled fluid, cools the panel preventing burring, smearing, and melting of metal contacts.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: October 22, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan
  • Patent number: 6452255
    Abstract: A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages that are arranged to have relatively low inductance are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the thinned die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed. In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: September 17, 2002
    Assignee: National Semiconductor, Corp.
    Inventors: Jaime Bayan, Peter Howard Spalding, Harry Cheng Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
  • Publication number: 20020100163
    Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Applicant: National Semiconductor Corporation
    Inventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
  • Patent number: 6399415
    Abstract: A variety of techniques for electrically debussing conductive substrate panels used in the formation of a matrix of leadless integrated circuit packages are described. Generally, after a matrix of leadless packages have been fabricated in panel form on a conductive substrate panel, tie bars that are used to support contacts and potentially other structures on the conductive substrate are removed after plastic caps have been molded over the matrix, but before separating the packaged devices. This serves to electrically isolate the contacts from one another while leaving sufficient portions of the molded substrate structure in tact to facilitate handling the structure in panel form. With the described arrangement, the packaged devices may be tested in panel form. After testing and any other desired panel based operations, the packaged devices may be separated using conventional techniques. The removal of the tie bars can be accomplished by any suitable technique including, for example, sawing or etching.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: June 4, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Jaime Bayan, Peter Howard Spalding, Harry Cheng Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong