Patents by Inventor Aharon Aharon

Aharon Aharon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6006028
    Abstract: An architecture-independent test program generator for producing test programs for checking the operation of a hardware processor design comprises means for storing data representing the processor instruction set and resources, and logic for generating, for subsequent storage or processing, test programs from said stored data, characterized in that the data is a separate declarative specification, the generator comprising logic for extracting said data from the storage means, and in that the relationships between the processor resources and semantic entities associated with each instruction are modelled in said declarative specification.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: December 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Aharon Aharon, Yossi Malka, Yossi Lichtenstein
  • Patent number: 5724504
    Abstract: A technique that applies the task coverage exercised within a behavioral model of the design to the design itself, while simulating one or more test sequences. Since the behavior model is an accurate and complete program representation of the architectural specification of the hardware design, the test case coverage of the architecture is implied by the measurement of how well the behavioral model code has been exercised. The completeness of the coverage is determined by the test coverage criteria selected, including, for example, statement coverage, branch coverage, or path coverage. The more detailed the criteria, the greater the number of tests.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Aharon Aharon, Laurent Fournier, Alon Gluska, Yossi Lichtenstein, Yossi Malka
  • Patent number: 5202889
    Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: April 13, 1993
    Assignee: International Business Machines Corporation
    Inventors: Aharon Aharon, Ayal Bar-David, Raanan Gewirtzman, Emanuel Gofman, Moshe Leibowitz, Victor Shwartzburd