Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.

Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

Abstract: A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.

Abstract: Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a "0" being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.

Abstract: A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a "probe" request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the "probe" request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request.