Patents by Inventor AHIAD TURGEMAN

AHIAD TURGEMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective event logging
    Patent number: 10579611
    Abstract: An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 3, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Refael Ben-Rubi, Moshe Cohen, Ahiad Turgeman, Uri Shir, David Chaim Brief
  • Memory operation threshold adjustment based on bit line integrity data
    Patent number: 10162538
    Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mark Shlick, Refael Ben-Rubi, Uri Shir, Ahiad Turgeman, Uri Peltz
  • SELECTIVE EVENT LOGGING
    Publication number: 20180349429
    Abstract: An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Inventors: REFAEL BEN-RUBI, MOSHE COHEN, AHIAD TURGEMAN, URI SHIR, DAVID CHAIM BRIEF
  • MEMORY OPERATION THRESHOLD ADJUSTMENT BASED ON BIT LINE INTEGRITY DATA
    Publication number: 20170090788
    Abstract: A data storage device includes a controller and a memory. The memory is coupled to the controller. The memory includes storage elements coupled to bit lines. The controller is configured to access bit line integrity data corresponding to a region of the memory, the bit line integrity data indicating a number of bit lines. The controller is also configured to store data related to a memory operation threshold based on the number of bit lines.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: MARK SHLICK, REFAEL BEN-RUBI, URI SHIR, AHIAD TURGEMAN, URI PELTZ