Patents by Inventor Ahila Krishnamoorthy

Ahila Krishnamoorthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170133650
    Abstract: Disclosed herein are soluble content absorbent glass mats or AGM separators for VRLA, AGM, or VRLA AGM batteries. Such glass mats may be prepared from insoluble glass fibers blended with soluble content materials. Upon exposure to a suitable solvent, the dissolving or solvating of the soluble content produces voids within the glass mat. The voids enhance the absorption of the solvent within the glass mat. The soluble content may be acid-soluble glass fibers or microfibers.
    Type: Application
    Filed: June 24, 2016
    Publication date: May 11, 2017
    Inventors: Ahila Krishnamoorthy, Daniel R. Alexander
  • Publication number: 20170104199
    Abstract: Improved battery separators are disclosed herein for use in flooded lead-acid batteries, and in particular enhanced flooded lead-acid batteries. The improved separators disclosed herein provide for enhanced electrolyte mixing and substantially reduced acid stratification. The improved flooded lead-acid batteries may be advantageously employed in applications in which the battery remains in a partial state of charge, for instance in start/stop vehicle systems. Also, improved lead-acid batteries, such as flooded lead-acid batteries, improved systems that include a lead-acid battery and a battery separator, improved battery separators, improved vehicles including such systems, and/or methods of manufacture and/or use may be provided.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 13, 2017
    Inventors: Eric H. Miller, M. Neal Golovin, Ahila Krishnamoorthy, Matthew Howard, James P. Perry, J. Kevin Whear
  • Publication number: 20170098810
    Abstract: In accordance with at least selected embodiments, the present application or invention is directed to novel or improved porous membranes or substrates, separator membranes, separators, composites, electrochemical devices, batteries, methods of making such membranes or substrates, separators, and/or batteries, and/or methods of using such membranes or substrates, separators and/or batteries. In accordance with at least certain embodiments, the present application is directed to novel or improved porous membranes having a coating layer, battery separator membranes having a coating layer, separators, energy storage devices, batteries, including lead acid batteries including such separators, methods of making such membranes, separators, and/or batteries, and/or methods of using such membranes, separators and/or batteries.
    Type: Application
    Filed: October 5, 2016
    Publication date: April 6, 2017
    Inventors: J. Kevin Whear, Ahila Krishnamoorthy, Susmitha Appikatla
  • Publication number: 20150170820
    Abstract: Magnetic component assemblies for circuit boards include single, shaped magnetic core pieces formed with a physical gap and conductive windings assembled to the cores via the gaps. The physical gaps in the cores are filled with an expandable magnetic material to eliminate minute non-magnetic gaps and enhance magnetic performance. The magnetic component assemblies may define power inductors.
    Type: Application
    Filed: November 24, 2014
    Publication date: June 18, 2015
    Inventors: Abdul Kadir, Ahila Krishnamoorthy
  • Patent number: 8901268
    Abstract: Crosslinkable compositions are disclosed herein that comprise at least one silicon-based material comprising at least one alkyl group and at least one aryl or aromatic group, at least one catalyst, and at least one solvent.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: December 2, 2014
    Inventors: Ahila Krishnamoorthy, Richard Spear, Amanuel Gebrebrhan
  • Patent number: 8859673
    Abstract: Polymer formulations are disclosed and described herein that comprise: at least one polymer comprising at least one hydroxy functional group, at least one acid source, and at least one acid-activated crosslinker that reacts with the polymer. In contemplated embodiments, these polymer formulations are curable at relatively low temperatures, as compared to those polymer formulations not comprising contemplated crosslinkers. Transparent films formed from these contemplated formulations are also disclosed. Organic transparent film compositions are also disclosed that comprise: at least one at least one phenol-based polymer, at least one solvent; at least one acid-activated crosslinker; and at least one acid source. Methods of forming organic transparent films with improved transmittance by depositing on a substrate the formulations disclosed herein and curing the formulations or compositions at a temperature of less than about 200° C.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: October 14, 2014
    Assignee: Honeywell International, Inc.
    Inventors: Edward Rutter, Jr., Ahila Krishnamoorthy, Joseph Kennedy
  • Publication number: 20140266555
    Abstract: Magnetic component assemblies for circuit boards include magnetic cores formed with a gap and preformed conductive windings sliding assembled to the cores via the gaps. The gaps in the cores are filled with a magnetic material to enhance the magnetic performance. The magnetic component assemblies may define power inductors.
    Type: Application
    Filed: January 3, 2014
    Publication date: September 18, 2014
    Inventors: Ahila Krishnamoorthy, Robert James Bogert, Yipeng Yan
  • Publication number: 20140266539
    Abstract: Magnetic component assemblies for circuit boards include single, shaped magnetic core pieces formed with a physical gap and conductive windings assembled to the cores via the gaps. The physical gaps in the cores are filled with a magnetic material to enhance the magnetic performance. The magnetic component assemblies may define power inductors.
    Type: Application
    Filed: January 3, 2014
    Publication date: September 18, 2014
    Inventors: Ahila Krishnamoorthy, Robert James Bogert, Yipeng Yan
  • Publication number: 20110171447
    Abstract: Crosslinkable compositions are disclosed herein that comprise at least one silicon-based material comprising at least one alkyl group and at least one aryl or aromatic group, at least one catalyst, and at least one solvent.
    Type: Application
    Filed: February 6, 2008
    Publication date: July 14, 2011
    Inventors: Ahila Krishnamoorthy, Richard Spear, Amanuel Gebrebrhan
  • Publication number: 20110054119
    Abstract: Polymer formulations are disclosed and described herein that comprise: at least one polymer comprising at least one hydroxy functional group, at least one acid source, and at least one acid-activated crosslinker that reacts with the polymer. In contemplated embodiments, these polymer formulations are curable at relatively low temperatures, as compared to those polymer formulations not comprising contemplated crosslinkers. Transparent films formed from these contemplated formulations are also disclosed. Organic transparent film compositions are also disclosed that comprise: at least one at least one phenol-based polymer, at least one solvent; at least one acid-activated crosslinker; and at least one acid source. Methods of forming organic transparent films with improved transmittance by depositing on a substrate the formulations disclosed herein and curing the formulations or compositions at a temperature of less than about 200° C.
    Type: Application
    Filed: February 20, 2009
    Publication date: March 3, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Edward Rutter, Ahila Krishnamoorthy, Joseph Kennedy
  • Publication number: 20080157065
    Abstract: Optoelectronic devices are described that include: a) a surface within the device, and b) at least one sufficiently light-transmissive crosslinked film, wherein the film is formed from at least one silicon-based material, at least one catalyst, and at least one solvent. Optoelectronic device are also disclosed, which include: a) a surface within the device, and b) at least one light-transmissive crosslinkable composition, wherein the composition comprises at least one silicon-based material, at least one crosslinking agent and at least one solvent. Methods of producing optoelectronic devices are also disclosed that include: a) providing a surface, b) providing at least one sufficiently light-transmissive crosslinkable composition, wherein the composition comprises at least one silicon-based material and at least one catalyst, c) applying the crosslinkable material to the surface, and d) curing the crosslinkable material to form a sufficiently light-transmissive crosslinked composition.
    Type: Application
    Filed: April 10, 2007
    Publication date: July 3, 2008
    Inventors: Ahila Krishnamoorthy, Joseph Kennedy, Richard Spear, Deborah Yellowaga, Peter Smith, Ben Palmer, Ronald Katsanes, Michael Tucker
  • Patent number: 7202159
    Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 10, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Ramanath Ganapathiraman, Ahila Krishnamoorthy, Kaushik Chanda, Shyam P. Murarka
  • Patent number: 6913994
    Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Agency for Science, Technology and Research
    Inventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov
  • Publication number: 20040203223
    Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top comers of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: Institute of Microelectronics
    Inventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov
  • Publication number: 20040180506
    Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 16, 2004
    Inventors: G. Ramanath, Ahila Krishnamoorthy, Kaushik Chanda, Shyam P. Murarka
  • Patent number: 6486533
    Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: November 26, 2002
    Assignee: Semitool, Inc.
    Inventors: Ahila Krishnamoorthy, David J. Duquette, Shyam P. Murarka
  • Publication number: 20020105081
    Abstract: The present invention provides a diffusion barrier in an integrated circuit. The diffusion barrier comprises a self-assembled monolayer. The diffusion barrier is preferably less than 5 nm thick; more preferably it is less than 2 nm thick. The self-assembled monolayer typically contains an aromatic group at its terminus.
    Type: Application
    Filed: October 11, 2001
    Publication date: August 8, 2002
    Inventors: G. Ramanath, Ahila Krishnamoorthy, Kaushik Chanda, Shyam P. Murarka
  • Publication number: 20020079487
    Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.
    Type: Application
    Filed: October 11, 2001
    Publication date: June 27, 2002
    Inventors: G. Ramanath, Ahila Krishnamoorthy, Kaushik Chanda, Shyam P. Murarka
  • Publication number: 20020050628
    Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.
    Type: Application
    Filed: November 21, 2001
    Publication date: May 2, 2002
    Applicant: Semitool, Inc.
    Inventors: Ahila Krishnamoorthy, David J. Duquette, Shyam P. Murarka
  • Patent number: 6368966
    Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: April 9, 2002
    Assignee: Semitool, Inc.
    Inventors: Ahila Krishnamoorthy, David J. Duquette, Shyam P. Murarka