Abstract: A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.

Abstract: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M?1]) and receiving M correction bits (c[0], . . . , c[M?1]) and L address bits (a[0], . . . , a[L?1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.

Abstract: Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for the selected decoder configuration. When F=Ø, a set of patterns Pi is reported for each decoder configuration i?C, where C is a set of selected decoder configurations.