Patents by Inventor Ahmad Abdo
Ahmad Abdo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818242Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.Type: GrantFiled: September 10, 2020Date of Patent: November 14, 2023Inventors: Ahmad Abdo, Shahab Oveis Gharan, Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw
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Patent number: 11770203Abstract: Systems and methods for controlling network configurations or assignments are provided. A method, according to one implementation, includes a step of calculating transmission characteristics between each pair of a plurality of pairs of modems at opposite ends of a Dense Wavelength-Division Multiplexing (DWDM) transport link using specifications of the modems measured during production. The method also includes the step of selecting a pair of modems from the plurality of pairs of modems based on results obtained by calculating the transmission characteristics and based on one or more user-defined service requests.Type: GrantFiled: September 9, 2021Date of Patent: September 26, 2023Assignee: Ciena CorporationInventors: Khaled Maamoun, Ahmad Abdo, Sadok Aouini, Bilal Riaz, Mahdi Parvizi
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Publication number: 20230074349Abstract: Systems and methods for controlling network configurations or assignments are provided. A method, according to one implementation, includes a step of calculating transmission characteristics between each pair of a plurality of pairs of modems at opposite ends of a Dense Wavelength-Division Multiplexing (DWDM) transport link using specifications of the modems measured during production. The method also includes the step of selecting a pair of modems from the plurality of pairs of modems based on results obtained by calculating the transmission characteristics and based on one or more user-defined service requests.Type: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Inventors: Khaled Maamoun, Ahmad Abdo, Sadok Aouini, Bilal Riaz, Mahdi Parvizi
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Publication number: 20220222865Abstract: A system and method for compressing and decompressing image data, which provides better compression and minimal representation of the input image with minimal loss compared to previous Deep Learning codecs. The system can provide for quantization during training, flexible addition of filters, and conditional complexity of image compression. The Deep Learning codec generates codes that are directly usable with Machine Learning algorithms, thus boosting the performance of Machine Learning algorithms.Type: ApplicationFiled: January 10, 2022Publication date: July 14, 2022Inventors: OMAR AHMAD ABDO AL TAMIMI, Tareq Aljaber
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Patent number: 11349486Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: GrantFiled: February 25, 2020Date of Patent: May 31, 2022Assignee: Ciena CorporationInventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Publication number: 20220149847Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: ApplicationFiled: February 25, 2020Publication date: May 12, 2022Inventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Patent number: 10985900Abstract: Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.Type: GrantFiled: March 3, 2020Date of Patent: April 20, 2021Assignee: Ciena CorporationInventors: Ahmad Abdo, Shahab Oveis Gharan, James Harley, Sadok Aouini, Timothy James Creasy, Naim Ben-Hamida
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Publication number: 20200412520Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Inventors: Ahmad Abdo, Shahab Oveis Gharan, Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Lukas Jakober, Yalmez M.A. Yazaw
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Patent number: 10855380Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.Type: GrantFiled: February 7, 2019Date of Patent: December 1, 2020Assignee: Ciena CorporationInventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo
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Publication number: 20200344038Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Inventors: Sadok Aouini, Naim Ben-Hamida, Ahmad Abdo, Timothy James Creasy, Lukas Jakober, Yalmez M.A. Yazaw, Shahab Oveis Gharan
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Patent number: 10805064Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).Type: GrantFiled: April 23, 2019Date of Patent: October 13, 2020Assignee: Ciena CorporationInventors: Sadok Aouini, Naim Ben-Hamida, Ahmad Abdo, Timothy James Creasy, Lukas Jakober, Yalmez M. A. Yazaw, Shahab Oveis Gharan
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Publication number: 20200274537Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: ApplicationFiled: December 23, 2019Publication date: August 27, 2020Inventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Patent number: 10749536Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: GrantFiled: December 23, 2019Date of Patent: August 18, 2020Assignee: Ciena CorporationInventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Patent number: 10516403Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.Type: GrantFiled: February 27, 2019Date of Patent: December 24, 2019Assignee: Ciena CorporationInventors: Sadok Aouini, Naim Ben-Hamida, Timothy James Creasy, Ahmad Abdo, Mahdi Parvizi, Lukas Jakober
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Publication number: 20190190617Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Inventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo
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Patent number: 10243671Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.Type: GrantFiled: October 27, 2017Date of Patent: March 26, 2019Assignee: Ciena CorporationInventors: Sadok Aouini, Bilal Riaz, Naim Ben-Hamida, Lukas Jakober, Ahmad Abdo