Patents by Inventor Ahmad Ashrafzadeh
Ahmad Ashrafzadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142538Abstract: A method for measuring electrical quantities in an electrical system includes obtaining a first set of known electrical outputs of an electrical quantity sensor at a first temperature. The method also includes obtaining a second set of known electrical outputs of the electrical quantity sensor at a second temperature that is different from the first temperature. The method further includes measuring an operational temperature of one or more locations in the electrical system. The method still further includes computing a pair of reference electrical output values corresponding to the measured operational temperature in accordance with the first set of known electrical outputs at the first temperature and the second set of known electrical outputs at the second temperature.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventor: Ahmad Ashrafzadeh
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Patent number: 11906597Abstract: A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital convertors for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.Type: GrantFiled: January 27, 2021Date of Patent: February 20, 2024Assignee: NOVA SEMICONDUCTOR, INC.Inventor: Ahmad Ashrafzadeh
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Publication number: 20210151834Abstract: A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital convertors for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.Type: ApplicationFiled: January 27, 2021Publication date: May 20, 2021Inventor: Ahmad ASHRAFZADEH
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Patent number: 10964928Abstract: A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital converters for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.Type: GrantFiled: November 2, 2018Date of Patent: March 30, 2021Assignee: Nova Semiconductor, Inc.Inventor: Ahmad Ashrafzadeh
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Patent number: 10446498Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: GrantFiled: August 14, 2017Date of Patent: October 15, 2019Assignee: Fairchild Semiconductor CorporationInventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
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Patent number: 10304758Abstract: Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.Type: GrantFiled: March 7, 2013Date of Patent: May 28, 2019Assignee: MAXIM INTEGRATED PRODUCTS, INCInventors: Karthik Thambidurai, Ahmad Ashrafzadeh, Viresh P. Patel, Viren Khandekar
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Publication number: 20190148701Abstract: A resistor ladder comprising identical resistors is disposed electrically in parallel with a multicell battery to calibrate voltage-controlled oscillators or analog-to-digital convertors for voltage balancing the battery cells in the multicell battery. Switches in a first state provide the voltage across each resistor as inputs to the VCOs or ADCs. The number of oscillations of the output signal of each VCO or ADC over a predetermined time period are compared to determine an offset error. Switches in a second state provide the voltage across each battery cell as inputs to the VCOs or ADCs. The battery cells with a higher relative voltage can be discharged until they are balanced. Some aspects describe temperature-adjusted and interpolated determinations of electrical quantities in the cells such as voltage and/or current.Type: ApplicationFiled: November 2, 2018Publication date: May 16, 2019Inventor: Ahmad Ashrafzadeh
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Publication number: 20170373008Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: ApplicationFiled: August 14, 2017Publication date: December 28, 2017Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
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Patent number: 9735112Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: GrantFiled: January 9, 2015Date of Patent: August 15, 2017Assignee: Fairchild Semiconductor CorporationInventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
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Patent number: 9472451Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.Type: GrantFiled: October 13, 2014Date of Patent: October 18, 2016Assignee: Maxim Integrated Products, Inc.Inventors: Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Amit S. Kelkar, Hien D. Nguyen
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Publication number: 20150200162Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: ApplicationFiled: January 9, 2015Publication date: July 16, 2015Inventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
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Publication number: 20150028475Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.Type: ApplicationFiled: October 13, 2014Publication date: January 29, 2015Inventors: Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Amit S. Kelkar, Hien D. Nguyen
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Publication number: 20140312458Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.Type: ApplicationFiled: November 27, 2013Publication date: October 23, 2014Applicant: Fairchild Semiconductor CorporationInventors: Ahmad ASHRAFZADEH, Vijay ULLAL, Justin CHIANG, Daniel KINZER, Michael M. DUBE, Oseob JEON, Chung-Lin WU, Maria Cristina ESTACIO
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Patent number: 8860222Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.Type: GrantFiled: November 30, 2012Date of Patent: October 14, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Viren Khandekar, Karthik Thambidurai, Ahmad Ashrafzadeh, Amit Kelkar, Hien D. Nguyen
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Patent number: 8629499Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.Type: GrantFiled: May 28, 2012Date of Patent: January 14, 2014Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad Ashrafzadeh
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Publication number: 20120292691Abstract: A MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.Type: ApplicationFiled: May 28, 2012Publication date: November 22, 2012Inventor: Ahmad Ashrafzadeh
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Patent number: 8188541Abstract: In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.Type: GrantFiled: February 25, 2011Date of Patent: May 29, 2012Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad Ashrafzadeh
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Publication number: 20110227153Abstract: In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.Type: ApplicationFiled: February 25, 2011Publication date: September 22, 2011Applicant: Maxim Integrated Products, Inc.Inventor: Ahmad Ashrafzadeh
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Patent number: 7969002Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.Type: GrantFiled: October 29, 2008Date of Patent: June 28, 2011Assignee: Maxim Integrated Products, Inc.Inventors: Ahmad Ashrafzadeh, Mansour Izadinia, Nitin Kalje, Ignacio McQuirk
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Patent number: 7910992Abstract: In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface.Type: GrantFiled: July 15, 2008Date of Patent: March 22, 2011Assignee: Maxim Integrated Products, Inc.Inventor: Ahmad Ashrafzadeh