Abstract: Embodiments are disclosed for a quantum key distribution (QKD) enabled intra-datacenter network. An example system includes a first QKD device and a second QKD device. The first QKD device includes a first quantum-enabled port and a first network port. The second QKD device includes a second quantum-enabled port and a second network port. The first quantum-enabled port of the first QKD device is communicatively coupled to the second quantum-enabled port of the second QKD device via a QKD link associated with quantum communication. Furthermore, the first network port of the first QKD device is communicatively coupled to a first network switch via a first classical link associated with classical network communication. The second network port of the second QKD device is communicatively coupled to a second network switch via a second classical link associated with classical network communication.

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

Abstract: Embodiments are disclosed for a quantum key distribution (QKD) enabled intra-datacenter network. An example system includes a first QKD device and a second QKD device. The first QKD device includes a first quantum-enabled port and a first network port. The second QKD device includes a second quantum-enabled port and a second network port. The first quantum-enabled port of the first QKD device is communicatively coupled to the second quantum-enabled port of the second QKD device via a QKD link associated with quantum communication. Furthermore, the first network port of the first QKD device is communicatively coupled to a first network switch via a first classical link associated with classical network communication. The second network port of the second QKD device is communicatively coupled to a second network switch via a second classical link associated with classical network communication.

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

Abstract: Apparatus having a firmware memory storing firmware, a cache memory loading at least part of the firmware for execution by a processor, and a firmware checking engine having a defined syndrome storage location and performing the following iteratively on cache line entries associated with the firmware stored in the cache memory: choose a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare a content of the cache line entry to a content of a corresponding address in the firmware stored in the firmware memory, and produce an integrity result indicating whether integrity of the apparatus has been compromised.

Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.

Abstract: Apparatus having a firmware memory storing firmware, a cache memory loading at least part of the firmware for execution by a processor, and a firmware checking engine having a defined syndrome storage location and performing the following iteratively on cache line entries associated with the firmware stored in the cache memory: choose a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare a content of the cache line entry to a content of a corresponding address in the firmware stored in the firmware memory, and produce an integrity result indicating whether integrity of the apparatus has been compromised. The abstract is not meant to be limiting.

Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.