Abstract: In one example, a semiconductor device includes an acoustic medium, a first transducer on the acoustic medium, a first electrode coupled to the first transducer, a second transducer on the acoustic medium, and a second electrode coupled to the second acoustic transducer. The semiconductor device also includes a semiconductor substrate to support the acoustic medium and first and second transducers. Mold compound encapsulates at least a portion of the acoustic medium, the first acoustic transducer, the second acoustic transducer, and the semiconductor substrate.

Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: A clock reference includes a substrate, a first resonator and a second resonator both formed on the substrate providing a differential resonator pair. A first variable capacitor is connected across electrodes of the first resonator for electronically tuning a first native frequency of the first resonator to provide a first tuned frequency (f1) and a second variable capacitor is connected across electrodes of the second resonator for electronically tuning a second native frequency of the second resonator to provide a second tuned frequency (f2). A frequency mixer is coupled to receive f1 and f2 for generating a frequency difference signal.

Abstract: A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The method includes, for a given IIR path for a received signal, updating gain of the given IIR path using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation; and updating a time constant of the given IIR path using a respective monitor tap error-data correlation with a second LMS update equation.

Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

Abstract: A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The method includes, for a given IIR path for a received signal, updating gain of the given IIR path using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation; and updating a time constant of the given IIR path using a respective monitor tap error-data correlation with a second LMS update equation.

Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract: A system configured to actively balance power among power cells such as batteries. The system includes a power module of series-coupled power cells, each exhibiting different charge levels during charging and discharging. A power module includes active cell balancing circuitry configured to substantially balance the charges of the power cells at least during charging. In one embodiment, the active cell balancing circuitry includes: (a) current source circuitry configured to supply extra charging current to a selected power cell; and (b) current source control circuitry configured to control the current source circuitry to supply extra charging current to the power cell with the lowest state of charge. In another embodiment, the system includes multiple power modules, each having multiple power cells coupled in series, and each having an active cell balancing circuit configured to substantially balance the charges of the power cells in an associated one of the power modules.

Abstract: A method for controlling heat dissipated from a prosthetic retinal device is described. A heat transfer device employs the Peltier heat transfer effect to cool the surface of the retinal device that faces the retina by dissipating/transferring collected heat away from the retina and towards the iris or front of the eye. According to one embodiment, a heat pump is formed in a second substrate on the retinal device. The heat pump is controlled by a temperature sense device that activates the heat pump, when a first predetermined temperature limit is exceeded. The temperature sense device deactivates the heat pump, when a temperature of the retinal device drops below a second predetermined temperature. According to another embodiment, a supply current of the retinal device may pass through the heat pump and a direction of heat transfer by the heat pump can be reversed, when the first predetermined temperature is exceeded.

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract: A system includes multiple speakers arranged in a speaker array configuration. The system also includes one or more filters configured to filter audio signals and generate filtered audio signals. The one or more filters are configured to operate using filter coefficients associated with a desired beam pattern to be produced by the multiple speakers. The system further includes at least one amplifier configured to amplify the filtered audio signals and provide the amplified filtered audio signals to the speakers. The one or more filters reside within or are coupled to the at least one amplifier. The system may further include a controller configured to modify at least one of the filter coefficients based on a change in the speaker configuration. The filters may operate independently of a centralized processor, and a centralized processor may not even be required to provide electronic beam forming.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.