Abstract: One example discloses a power application circuit, including: a first power application circuit, configured to receive an enable signal and a first voltage; wherein the first power application circuit is configured to output the first voltage at a first current after a first delay from when the enable signal is received; and a second power application circuit, configured to receive the enable signal and a second voltage; wherein the second power application circuit is configured to output the second voltage at a second current after a second delay from when the enable signal is received.

Abstract: One example discloses a power application circuit, including: a first power application circuit, configured to receive an enable signal and a first voltage; wherein the first power application circuit is configured to output the first voltage at a first current after a first delay from when the enable signal is received; and a second power application circuit, configured to receive the enable signal and a second voltage; wherein the second power application circuit is configured to output the second voltage at a second current after a second delay from when the enable signal is received.

Abstract: Various embodiments relate to a protection circuit, comprising: a pad configured to input an external voltage from a connector; a first circuit branch connected to the pad and configured to receive a fast ramp-up over voltage at the pad; a second circuit branch connected to the pad and configured to receive a ramp-up over voltage at the pad; a third circuit branch connected to the pad and configured to output an over voltage detection signal when an over voltage is received at the pad, wherein the third circuit branch includes a voltage divider with a variable resistor with a variable voltage node and an enable switch; and a logic circuit including an enabling transistor configured to control the variable resistor and the enable switch.

Abstract: Various embodiments relate to a protection circuit, comprising: a pad configured to input an external voltage from a connector; a first circuit branch connected to the pad and configured to receive a fast ramp-up over voltage at the pad; a second circuit branch connected to the pad and configured to receive a ramp-up over voltage at the pad; a third circuit branch connected to the pad and configured to output an over voltage detection signal when an over voltage is received at the pad, wherein the third circuit branch includes a voltage divider with a variable resistor with a variable voltage node and an enable switch; and a logic circuit including an enabling transistor configured to control the variable resistor and the enable switch.

Abstract: A voltage detection circuit including an input voltage stage configured to scale down an input voltage to produce a scaled down voltage, a gain loss stage configured to receive and adjust the scaled down voltage based on a determined gain or loss to be applied to the scaled down voltage, and a comparison circuit configured to determine if the input voltage is over or under a desired voltage value.

Abstract: A voltage detection circuit including an input voltage stage configured to scale down an input voltage to produce a scaled down voltage, a gain loss stage configured to receive and adjust the scaled down voltage based on a determined gain or loss to be applied to the scaled down voltage, and a comparison circuit configured to determine if the input voltage is over or under a desired voltage value.

Abstract: An over-voltage protection circuit and method may include a pass gate and a voltage boosting circuit for providing protection to start-up voltage-sensitive circuits during start-up conditions of a system including the voltage-sensitive circuits. The pass gate may include a drain, source, and gate, with the drain configured to receive an input signal and the source configured to output the input signal, in response to a pass gate driving voltage signal applied to the gate of the pass gate. The voltage boosting circuit may include an output coupled to the gate of the pass gate, the voltage boosting circuit configured to generate a pass gate driving voltage on the output. The voltage boosting circuit further configured to passively control the pass gate driving voltage to a level less than a steady-state voltage level during start-up of the protection circuit.

Abstract: A startup circuit for a voltage reference circuit is provided. The startup circuit includes first, second, and third transistors. The first transistor has a first current electrode coupled to the voltage reference circuit, a control electrode, and a second current electrode coupled to a ground terminal. The second transistor has a first current electrode and a control electrode both coupled to a power supply voltage terminal, and a second current electrode. The third transistor has a first current electrode coupled to the second current electrode of the second transistor and to the control electrode of the first transistor, a control electrode coupled to the voltage reference circuit, and a second current electrode coupled to the ground terminal. During application of a power supply voltage, the second transistor is off, thus providing only a leakage current to the gate of the first transistor. This provides for reliable startup with very low residual current after startup is complete.

Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.

Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.

Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.

Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.

Abstract: An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively.

Abstract: An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT 1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively.

Abstract: A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on relatively small-value signals and alternative circuitry for amplifying/processing signals during a condition which otherwise would cause thermal imbalance in the main circuitry. The circuit stage includes switching circuitry for coupling signals in the signal path of the input signal to the main input circuitry during normal small-signal operating conditions and for coupling signals in the signal path of the input signal to the alternative circuitry during the condition which otherwise would cause thermal imbalance in the main circuitry.

Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on relatively small-value signals and alternative circuitry for amplifying/processing signals during a condition which otherwise would cause thermal imbalance in the main circuitry. The circuit stage includes switching circuitry for coupling signals in the signal path of the input signal to the main input circuitry during normal small-signal operating conditions and for coupling signals in the signal path of the input signal to the alternative circuitry during the condition which otherwise would cause thermal imbalance in the main circuitry.

Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.

Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.