Abstract: A control loop for a clocked switching power converter where the loop features a comparator (44) and a filter (61) in series to linearize the nonlinear response of the comparator (44). The filter (61) has poles and zeros offsetting the poles and zeros of a bridge rectifier (M1 and M2).

Abstract: A power-supply-independent clock, with controlled THigh and TLow that permits both frequency and duty cycle to be set simultaneously and independently. Depending upon the implementation, the control values can be varied for frequency and duty cycle as determined by the user, or can be dependent upon temperature, power supply variations, or any other variable within the system, design or device that includes the clock.

Abstract: A design and method for controlling the initial inductor current in a DC/DC switching regulator. The Ton or Toff time, depending upon implementation, is gradually increased such that power applied to a load is initially constrained until the system reaches a stable state, at which time normal power is connected to the load. In an embodiment, the on or off time is limited by a circuit which controls a pair of complementary transistors. The states of the transistors are controlled by the use of a startup-phase voltage and a reference voltage, which are then compared in an error amplifier. The result of the comparison is compared to a sawtooth signal in a comparator, the output of which controls the state of complementary transistors.

Abstract: A control loop for a clocked switching power converter where the loop features a comparator (44) and a filter (61) in series to linearize the nonlinear response of the comparator (44). The filter (61) has poles and zeros offsetting the poles and zeros of a bridge rectifier (M1 and M2).

Abstract: An adjustable duty-cycle circuit includes an EXCLUSIVE-OR circuit for combining a divided reference input signal at a frequency .function..sub.IN /2 with a variably delayed divided reference input signal to provide an output frequency V.sub.O at .function..sub.IN with an adjustable duty cycle. A variable delay circuit, or delay line, is controlled by a control signal which is generated by comparing a signal equal to the average (DC) value of V.sub.O with an adjustable DC reference signal from a voltage divider or a DAC. An output signal from the comparator is filtered to provide the control signal V.sub.C for the delay circuit to control the duty cycle of the output signal. To provide a frequency doubler, the reference input signal is not divided by two to thereby obtain an output signal at 2.function..sub.IN with an adjustable duty cycle. Frequency multipliers for N=3, 5, 7, etc. are implemented with additional delays and exclusive logic circuits.