Patents by Inventor Ahmad Khairi

Ahmad Khairi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756747
    Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Roee Eitan, Ram Livne, Ahmad Khairi, Yoel Krupnik, Ariel Cohen
  • Publication number: 20190326922
    Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Roee Eitan, Ram Livne, Ahmad Khairi, Yoel Krupnik, Ariel Cohen
  • Patent number: 10340938
    Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Roee Eitan, Ram Livne, Ahmad Khairi, Yoel Krupnik, Ariel Cohen