Patents by Inventor Ahmed A. Emira

Ahmed A. Emira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111748
    Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Ayman Mohamed ELSAYED, Ahmed EMIRA, Rami H. KHATIB, Janakan SIVASUBRAMANIAM, Jared M. GAGNE
  • Patent number: 10965295
    Abstract: A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: March 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Faisal Hussien, Ahmed Emira, Esmail Babakrpur Nalousi
  • Patent number: 10958275
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Patent number: 10938296
    Abstract: Techniques are described for ripple detection and cancellation in switching voltage regulator circuits. For example, in a switching voltage converter, a voltage is up-converted or down-converted by switching high side and low side switches and passed through a low-pass filter for averaging. While the act of switching can result in conversion of the voltage with good efficiency, it also typically generates ripples on the output voltage, which can be undesirable in some applications. Embodiments use the switching voltage, the output voltage, and a feed-forward loop to generate a current cancellation signal to have particular gain, timing, and polarity that effectively emulates the complement of the inductor ripple current. The cancellation current signal can be injected into the output node, such that the cancellation current signal sums with the inductor ripple current at the output node, thereby at least partially cancelling the effect of the inductor ripple current.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: March 2, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Siavash Yazdi, Ahmed Emira
  • Patent number: 10924121
    Abstract: A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 16, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
  • Patent number: 10911091
    Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 2, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Rami Khatib, Janakan Sivasubramaniam, Jared Gagne
  • Patent number: 10901009
    Abstract: Techniques are described for power detection of an amplified signal. For example, power detection described herein can receive an amplified signal from a power amplifier, and can generate an output signal that can be fed back to help regulate an output level of the power amplifier. Embodiments receive the amplified signal can be received by a transistor. A first measurement can be obtained at the transistor's emitter corresponding to an average bias level of the amplified signal, and a second measurement can be obtained at the transistor's base. The output signal can be generated as a function of a difference between the two measurements. Some embodiments further compensate for a measured effective diode voltage corresponding to a base-emitter voltage. Such an approach can generate the power detector output signal to be independent of the ? of the transistor, and therefore less affected by variations in process corners and temperature.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 26, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Rami Khatib, Ahmed Emira
  • Patent number: 10877504
    Abstract: A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 29, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Hassan Elwan
  • Patent number: 10879916
    Abstract: Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Faisal Hussien
  • Patent number: 10879915
    Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 29, 2020
    Assignee: GOODIX TECHNOLOGY INC.
    Inventors: Ahmed Emira, Faisal Hussien, Esmail Babakrpur Nalousi
  • Patent number: 10873486
    Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: December 22, 2020
    Assignee: GOODIX TECHNOLOGY INC.
    Inventors: Mohamed Aboudina, Ahmed Emira, Esmail Babakrpur Nalousi
  • Publication number: 20200389176
    Abstract: Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Ahmed Emira, Faisal Hussien
  • Patent number: 10862425
    Abstract: Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 8, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Mounir Fares
  • Publication number: 20200343857
    Abstract: Techniques are described for tuning a resonant circuit using differential switchable capacitors. For example, embodiments can operate in context of a power amplifier with a tunable resonant output network. To tune the network, multiple differential switchable capacitors are provided in parallel. Each differential switchable capacitor can include a pair of capacitors, each coupled between a respective internal node and a respective differential terminal; and the internal nodes are selectively coupled or decoupled using a respective electronic switch (e.g., transistor). Switching on one of the differential switchable capacitors forms a capacitive channel having an associated capacitance. Each differential switchable capacitor can also include a switch network to selectively pull the internal nodes to a high or low voltage reference according to the selected operating mode.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Ahmed EMIRA, Mounir FARES
  • Publication number: 20200343856
    Abstract: Techniques are described for post-compensation of frequency drift due to changes in crystal oscillator temperature during operation. For example, a clock system is coupled with a crystal oscillator, and can use a reference clock signal from the crystal oscillator to generate an output clock signal using a clock generator. The clock system can monitor an electrical characteristic of a thermal component integrated with the oscillator, which it can map deterministically to a thermal value indicating a temperature of a crystal component of the oscillator. The clock system can then map the temperature deterministically to a frequency shift of the oscillator away from a nominal value. The clock system can then generate a post-compensation signal that directs the clock generator to shift the frequency of the clock output signal so as to compensate for at least a portion of the frequency drift.
    Type: Application
    Filed: September 19, 2019
    Publication date: October 29, 2020
    Inventors: Mohamed ABOUDINA, Ahmed EMIRA, Amr Abuellil
  • Publication number: 20200336112
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Publication number: 20200328754
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 15, 2020
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10763790
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 1, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Publication number: 20200271699
    Abstract: Techniques are described for power detection of an amplified signal. For example, power detection described herein can receive an amplified signal from a power amplifier, and can generate an output signal that can be fed back to help regulate an output level of the power amplifier. Embodiments receive the amplified signal can be received by a transistor. A first measurement can be obtained at the transistor's emitter corresponding to an average bias level of the amplified signal, and a second measurement can be obtained at the transistor's base. The output signal can be generated as a function of a difference between the two measurements. Some embodiments further compensate for a measured effective diode voltage corresponding to a base-emitter voltage. Such an approach can generate the power detector output signal to be independent of the ? of the transistor, and therefore less affected by variations in process corners and temperature.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Rami Khatib, Ahmed EMIRA
  • Patent number: 10742222
    Abstract: Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 11, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Ahmet Tekin, Hassan Osama Elwan, Janakan Sivasubramaniam