Abstract: Systems and methods for hardware-based asynchronous logging include: initiating first and second atomic regions on first and second cores of a central processing unit (CPU); and asynchronously logging data for the first atomic region and the second atomic region using the CPU by: asynchronously performing log persist operations (LPOs) to log an old data value from each atomic region; updating the old data value to a new data value from each atomic region; tracking dependencies between the first atomic region and the second atomic region using a memory controller; asynchronously performing data persist operations (DPOs) to persist the new data value for each atomic region; and committing the first atomic region and the second atomic region based on the dependencies using the memory controller of the CPU.

Abstract: Performing storage-free instruction cache hit prediction is disclosed herein. In some aspects, a processor comprises an instruction cache hit prediction circuit that is configured to detect that a first access by a branch predictor circuit to a branch target buffer (BTB) for a first instruction in an instruction stream results in a miss on the BTB. In response to detecting the miss, the instruction cache hit prediction circuit is further configured to generate a first instruction cache prefetch request for the first instruction. The instruction cache hit prediction circuit is also configured to transmit the first instruction cache prefetch request to a prefetcher circuit.

Abstract: Providing location-based prefetching in processor-based devices is disclosed. In this regard, a processor-based device comprises a location-based prefetcher circuit associated with a first cache memory device having a faster access time and a smaller capacity than a second cache memory device. The location-based prefetcher circuit identifies an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request, and determines a set and a way of the second cache memory device where data corresponding to the second memory address is stored. The location-based prefetcher circuit then stores, in a prefetcher array entry of a prefetcher array, the first memory address as a trigger memory address, and a set indicator and a way indicator of the set and the way, respectively, of the second cache memory device as a target identifier.

Abstract: Systems and methods for hardware-based asynchronous logging include: initiating first and second atomic regions on first and second cores of a central processing unit (CPU); and asynchronously logging data for the first atomic region and the second atomic region using the CPU by: asynchronously performing log persist operations (LPOs) to log an old data value from each atomic region; updating the old data value to a new data value from each atomic region; tracking dependencies between the first atomic region and the second atomic region using a memory controller; asynchronously performing data persist operations (DPOs) to persist the new data value for each atomic region; and committing the first atomic region and the second atomic region based on the dependencies using the memory controller of the CPU.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.