Abstract: A computer memory access controller receives load and store requests from a plurality of parallel execution pipelines and forms queues of store and load addresses. A comparator compares load addresses with store addresses in a store address queue and selects a store before load if an address match is found, but selects a load before a store if no address match is found.

Abstract: A computer system with parallel execution pipelines and a memory access controller has store address queues holding addresses for store operations, store data queues holding a plurality of data for storing in the memory and load address storage holding addresses for load operations, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.