Abstract: The present disclosure is directed towards a prefetch controller configured to communicate with a prefetch cache in order to increase system performance. In some embodiments, the prefetch controller may include an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller may further include a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller may further include a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller may also include an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache.

Abstract: A method for selectively transforming a multi-dimensional input array comprising D dimensions includes, with a computing system, determining a D-dimensional convolution of the input array at only selected points in the array, each the convolution being a function of a product of D one-dimensional kernels; determining partial convolutions at each dimension iteratively, an iterative determination of one of the partial convolutions being determined, in part, from a previous iterative determination; and collecting transformed values from the convolutions into the input array to form a transformed input array.

Abstract: A method for selectively transforming a multi-dimensional input array comprising D dimensions includes segmenting the input array into a number of sub-arrays with a computing system; determining a D-dimensional convolution of the input array at only selected points in each the sub-array, the convolution being a function of a product of D one-dimensional kernels; determining partial convolutions at each dimension iteratively, an iterative determination of one of the partial convolutions being determined, in part, from a previous iterative determination; collecting transformed sub-array values to form a transformed input array; and storing the transformed input array.

Abstract: The present disclosure is directed towards a prefetch controller configured to communicate with a prefetch cache in order to increase system performance. In some embodiments, the prefetch controller may include an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller may further include a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller may further include a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller may also include an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache.