Abstract: An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.

Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Abstract: A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (Ntm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.

Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Abstract: Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

Abstract: A method and system of controlling a power converter coupled between a power generator and an electric grid. The method comprises detecting a grid disturbance voltage dip event while the power converter operates in a first phase locked loop (PLL) control mode that establishes a state of synchronization with the electric grid, the power converter electrically coupled to either motor drive inverter or grid-tie inverter, detecting a loss of the state of synchronization with the electric grid in conjunction with progressive charge depletion from a charged state of the dc-link capacitors, switching the converter to a diode mode of operation, switching from the first PLL control mode to a second PLL control mode of operation of the power converter, and re-establishing the state of synchronization to timely pre-empt progressive depletion of charge from the dc-link capacitors while under the second PLL control mode of operation of the power converter.

Abstract: A method and system of controlling a power converter operatively coupled with an electric grid, includes: operating the power converter in a direct power control mode with a dynamic switching table, the dynamic switching table including a group of converter space vectors and switching rules associated with the grid voltage and the dc-link voltage of the power converter; detecting abnormalities in the grid voltage and/or the converter dc-link voltage due to a grid fault event relative to their nominal operating conditions; determining a group of crossover angles for a group of converter vectors including the nearest three vectors to a grid voltage vector location inside a hexagonal space vector diagram; dynamically selecting a proper vector based on algorithmic feedforward of the group of crossover angles to dynamically construct the dynamic switching table; and controlling an output power of the power converter.

Abstract: A method and system of controlling a power converter coupled between a power generator and an electric grid. The method comprises detecting a grid disturbance voltage dip event while the power converter operates in a first phase locked loop (PLL) control mode that establishes a state of synchronization with the electric grid, the power converter electrically coupled to either motor drive inverter or grid-tie inverter, detecting a loss of the state of synchronization with the electric grid in conjunction with progressive charge depletion from a charged state of the dc-link capacitors, switching the converter to a diode mode of operation, switching from the first PLL control mode to a second PLL control mode of operation of the power converter, and re-establishing the state of synchronization to timely pre-empt progressive depletion of charge from the dc-link capacitors while under the second PLL control mode of operation of the power converter.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: A method and system of controlling a power converter coupled between one of a motor drive inverter and a grid-tie inverter within an electric grid. The method comprises operating the power converter in a first PLL control mode that establishes a state of synchronization with the electric grid, detecting a grid disturbance voltage dip event; keeping the power converter synchronized and preserving charge of a set of dc-link capacitors, switching from the first PLL control mode to a second PLL control mode of operation of the power converter to obtain fast re-synchronization after dip period ends, and reverting to operation in the first PLL control mode upon re-establishing of the state of synchronization.

Abstract: A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.