Patents by Inventor Ahmed Elkholy

Ahmed Elkholy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250088196
    Abstract: A system may have a multiplexer and a controller. For a transition from a first pair of bits in first data provided to digital-to-analog converters (DACs) to a second pair of bits in second data, the controller may determine whether the transition is of a first type or of a second type, and in response to determining that the transition is of the first type, control the multiplexer to output the second pair of bits to the DACs. In response to determining that the transition is of the second type and the second pair of bits are to be swapped, the controller may control the multiplexer to output a swapped pair of bits to the DACs. Data output by the multiplexer based on the second data has a predetermined number of bits that have binary values different from those of corresponding bits in the first data.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 13, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Adesh Garg, Jun Cao
  • Publication number: 20250038755
    Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 30, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Jun Cao, Adesh Garg
  • Patent number: 12212342
    Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: January 28, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Yousr Ismail, Adesh Garg, Ali Nazemi, Jun Cao
  • Patent number: 12199608
    Abstract: An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: January 14, 2025
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Alireza Nilchi, Adesh Garg, Mohammad Elbadry, Ahmed Elkholy, Jun Cao
  • Patent number: 12119835
    Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: October 15, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Jun Cao, Adesh Garg
  • Publication number: 20240120905
    Abstract: An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 11, 2024
    Inventors: Alireza Nilchi, Adesh Garg, Mohammad Elbadry, Ahmed Elkholy, Jun Cao
  • Publication number: 20240120931
    Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Jun Cao, Adesh Garg
  • Publication number: 20230268929
    Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Yousr Ismail, Adesh Garg, Ali Nazemi, Jun Cao
  • Patent number: 11683048
    Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: June 20, 2023
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Yousr Ismail, Adesh Garg, Ali Nazemi, Jun Cao
  • Patent number: 11569830
    Abstract: A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (Ntm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 31, 2023
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Ahmed Elkholy, Adesh Garg
  • Publication number: 20220345152
    Abstract: Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Ahmed Elkholy, Yousr Ismail, Adesh Garg, Ali Nazemi, Jun Cao
  • Patent number: 11336226
    Abstract: Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 17, 2022
    Assignee: Si-Ware Systems SAE
    Inventors: David H. G. Mikhail, Ahmed Elkholy, Ahmed Helmy, Mohamed A. S. Eldin, Omar Essam El-Aassar, Nabil Sinoussi, Ahmed ElSayed, Mohamed Abd ElMoneim Bahry
  • Publication number: 20210026309
    Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 28, 2021
    Inventor: Ahmed Elkholy
  • Patent number: 10895850
    Abstract: A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: January 19, 2021
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Patent number: 10804914
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 13, 2020
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Patent number: 10707883
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: July 7, 2020
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Publication number: 20200212918
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventor: Ahmed Elkholy
  • Publication number: 20200186156
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Application
    Filed: January 29, 2020
    Publication date: June 11, 2020
    Inventor: Ahmed Elkholy
  • Publication number: 20200144964
    Abstract: Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: David H.G. Mikhail, Ahmed Elkholy, Ahmed Helmy, Mohamed A.S. Eldin, Omar Essam El-Aassar, Nabil Sinoussi, Ahmed ElSayed, Mohamed Abd ElMoneim Bahry
  • Patent number: 10644705
    Abstract: A method and system of controlling a power converter coupled between a power generator and an electric grid. The method comprises detecting a grid disturbance voltage dip event while the power converter operates in a first phase locked loop (PLL) control mode that establishes a state of synchronization with the electric grid, the power converter electrically coupled to either motor drive inverter or grid-tie inverter, detecting a loss of the state of synchronization with the electric grid in conjunction with progressive charge depletion from a charged state of the dc-link capacitors, switching the converter to a diode mode of operation, switching from the first PLL control mode to a second PLL control mode of operation of the power converter, and re-establishing the state of synchronization to timely pre-empt progressive depletion of charge from the dc-link capacitors while under the second PLL control mode of operation of the power converter.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 5, 2020
    Assignee: Emirates Steel Industries Co. PJSC
    Inventors: Hany Abdelmonem Hamed Ahmed, Ahmed Fathi Ahmed Abdou, Ehab Hassan Eid Bayoumi, Elwy Eissa Ahmed Elkholy