Patents by Inventor Ahmed Emira

Ahmed Emira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456731
    Abstract: An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: September 27, 2022
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Ahmed Emira, Mohamed Aboudina, Faisal Hussien
  • Publication number: 20220271723
    Abstract: A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.
    Type: Application
    Filed: June 17, 2021
    Publication date: August 25, 2022
    Inventors: Amr Abuellil, Faisal Hussien, Ayman Mohamed Elsayed, Ahmed Emira, Mohamed Aboudina
  • Patent number: 11405041
    Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: August 2, 2022
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
  • Patent number: 11356136
    Abstract: A receiver circuit includes a mixer receiving an RF signal encoding an information signal. The mixer receives a number of multiphase oscillator signals and generates multiphase baseband signals. The receiver circuit also includes a variable gain circuit receives the multiphase baseband signals, generates a first output signal having a first distortion, and a second output signal having a second distortion. The variable gain circuit is configured to generate a reduced distortion output signal based on the first and second output signals.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Ahmed Emira, Faisal Hussien, Mostafa Elmala, Mohamed Aboudina
  • Patent number: 11303250
    Abstract: An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.
    Type: Grant
    Filed: August 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Mostafa Elmala, Ahmed Emira, Mohamed Aboudina
  • Publication number: 20220077883
    Abstract: A receiver circuit includes a mixer receiving an RF signal encoding an information signal. The mixer receives a number of multiphase oscillator signals and generates multiphase baseband signals. The receiver circuit also includes a variable gain circuit receives the multiphase baseband signals, generates a first output signal having a first distortion, and a second output signal having a second distortion. The variable gain circuit is configured to generate a reduced distortion output signal based on the first and second output signals.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Inventors: Ahmed EMIRA, Faisal HUSSIEN, Mostafa ELMALA, Mohamed ABOUDINA
  • Publication number: 20220069774
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Publication number: 20220045650
    Abstract: An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.
    Type: Application
    Filed: August 9, 2020
    Publication date: February 10, 2022
    Inventors: Mostafa Elmala, Ahmed Emira, Mohamed Aboudina
  • Patent number: 11206030
    Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: December 21, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Faisal Hussien, Esmail Babakrpur Nalousi
  • Patent number: 11190141
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 11177988
    Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: November 16, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Esmail Babakrpur Nalousi
  • Patent number: 11171683
    Abstract: A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 9, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ayman Mohamed Elsayed, Ahmed Emira, Rami H Khatib, Janakan Sivasubramaniam, Jared M Gagne
  • Patent number: 11159186
    Abstract: A transmitter circuit is disclosed. The transmitter circuit includes a frequency circuit configured to generate a frequency signal, a power amplifier configured to drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal generated by the frequency circuit and the drive signal of the power amplifier. The programmable delay circuit is programmed with a programming value which causes the transmitter circuit to pass a calibration test.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 26, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Faisai Hussien, Esmail Babakrpur Nalousi
  • Patent number: 11139738
    Abstract: A converter circuit is disclosed. The converter circuit includes a controller configured to operate a pull up component and a pull down component so as to deliver power to a load through an inductor. The controller is configured to operate in either of first and second operational modes based on average current delivered to the load. The converter circuit also includes a mode control circuit configured to change operational modes in response to an indication of current flowing from the inductor to the switch node, and in response to an indication that the average current delivered to the load is greater than the current threshold.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: October 5, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Esmail Babakrpur Nalousi, Siavash Yazdi, Ahmed Emira
  • Publication number: 20210250031
    Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.
    Type: Application
    Filed: February 15, 2021
    Publication date: August 12, 2021
    Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
  • Publication number: 20210250030
    Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.
    Type: Application
    Filed: February 15, 2021
    Publication date: August 12, 2021
    Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
  • Publication number: 20210234737
    Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.
    Type: Application
    Filed: November 16, 2020
    Publication date: July 29, 2021
    Inventors: Mohamed Aboudina, Ahmed Emira, Esmail BABAKRPUR NALOUSI
  • Publication number: 20210234736
    Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 29, 2021
    Inventors: Mohamed ABOUDINA, Ahmed EMIRA, Esmail BABAKRPUR NALOUSI
  • Patent number: 11075578
    Abstract: A converter circuit includes a pull up component, a pull down component, and a controller configured to operate the pull up component and the pull down component so as to deliver power to a load. The controller is configured to operate the pull up and pull down components in first and second operational modes, based on an average current delivered to the load. The converter circuit also includes a mode control circuit to generate a mode control signal based in part on a representation of a peak current received at the switch node from the pull up component.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 27, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Siavash Yazdi, Esmail Babakrpur Nalousi, Ahmed Emira
  • Patent number: 11070225
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan