Abstract: In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

Abstract: Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Abstract: An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.

Abstract: Various methods and systems related to chaos-based pseudo-random number generation are presented. In one example, among others, a system includes a pseudo-random number generator (PRNG) to generate a series of digital outputs and a nonlinear post processing circuit to perform an exclusive OR (XOR) operation on a first portion of a current digital output of the PRNG and a permutated version of a corresponding first portion of a previous post processed output to generate a corresponding first portion of a current post processed output. In another example, a method includes receiving at least a first portion of a current output from a PRNG and performing an XOR operation on the first portion of the current PRNG output with a permutated version of a corresponding first portion of a previous post processed output to generate a corresponding first portion of a current post processed output.

Abstract: An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.

Abstract: In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

Abstract: Disclosed are various embodiments of methods and systems related to fractional order element based impedance matching. In one embodiment, a method includes aligning a traditional Smith chart (|?|=1) with a fractional order Smith chart (|?|?1). A load impedance is located on the traditional Smith chart and projected onto the fractional order Smith chart. A fractional order matching element is determined by transitioning along a matching circle of the fractional order Smith chart based at least in part upon characteristic line impedance. In another embodiment, a system includes a fractional order impedance matching application executed in a computing device. The fractional order impedance matching application includes logic that obtains a first set of Smith chart coordinates at a first order, determines a second set of Smith chart coordinates at a second order, and determines a fractional order matching element from the second set of Smith chart coordinates.

Abstract: Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Abstract: Disclosed are various embodiments of methods and systems related to fractional order element based impedance matching. In one embodiment, a method includes aligning a traditional Smith chart (|?|=1) with a fractional order Smith chart (|?|?1). A load impedance is located on the traditional Smith chart and projected onto the fractional order Smith chart. A fractional order matching element is determined by transitioning along a matching circle of the fractional order Smith chart based at least in part upon characteristic line impedance. In another embodiment, a system includes a fractional order impedance matching application executed in a computing device. The fractional order impedance matching application includes logic that obtains a first set of Smith chart coordinates at a first order, determines a second set of Smith chart coordinates at a second order, and determines a fractional order matching element from the second set of Smith chart coordinates.