Abstract: A computing system implementing a physical verification tool can identify edges of a geometric pattern located within a search area surrounding a point of interest in a semiconductor layout design, characterize the edges of the geometric pattern based on locations of center points of the edges from the point of interest within the search area, and generate geometrical feature vectors for the point of interest in the semiconductor layout design based on the characterization of the edges of the geometric pattern. The computing system can reconstruct the semiconductor layout design corresponding to the search area surrounding the point of interest using the geometrical feature vectors for the point of interest in the semiconductor layout design.

Abstract: System and methods for an edge-based camera are disclosed. Semiconductor layout designs are a representation of an integrated circuit that are used to manufacture the integrated circuit. Parts of the layout design, such as points of Interest (POIs), may be subject to analysis with regard to a downstream application, such as hotspot detection. Unlike pixel-based characterizations, POIs are characterized using topological features indicative of quantized values and dimensional features indicative of analog values. For example, an edge may be characterized using a set of relations, which characterizes corners and polygons (including the polygon on which the POI resides and external polygons). In turn, the set of relations may be used to define image representations, including images in different directions relative to the POI (including cardinal and ordinal image). In this way, the topological/dimensional characterization of the POI may be used to analyze the POI in the layout design.