Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.

Abstract: In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.

Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.

Abstract: In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.

Abstract: A circuit for driving an array of Light Emitting Diode (LED) strings at a constant current has a plurality of LEDs. A plurality of LED drivers is provided wherein a single LED driver is coupled to each of the plurality of LEDs. A voltage reference generator is used for sending a voltage reference signal to each LED driver. The voltage reference generator is external to each of the plurality of LED drivers. An input line voltage is coupled to the voltage reference generator. A clock generator is provided for sending to a clock signal to each of the plurality of LED drivers. The clock generator is external to each of the plurality of LED drivers. A low-frequency PWM dimming input signal is coupled to each of the plurality of LED drivers to allows dimming of the LEDs.

Abstract: A circuit for driving an array of Light Emitting Diode (LED) strings at a constant current has a plurality of LEDs. A plurality of LED drivers is provided wherein a single LED driver is coupled to each of the plurality of LEDs. A voltage reference generator is used for sending a voltage reference signal to each LED driver. The voltage reference generator is external to each of the plurality of LED drivers. An input line voltage is coupled to the voltage reference generator. A clock generator is provided for sending to a clock signal to each of the plurality of LED drivers. The clock generator is external to each of the plurality of LED drivers. A low-frequency PWM dimming input signal is coupled to each of the plurality of LED drivers to allows dimming of the LEDs.

Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.