Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

Abstract: One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a test system formatter including: a plurality of event logic interfaces, each event logic interface capable of receiving and decoding timing signals; a plurality of delay line elements (DLEs), each DLE being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from the corresponding event logic interface; drive logic coupled to the plurality of DLEs, having first and second outputs and operative to produce first and second formatted levels on the first and second outputs in response to timing markers received from the plurality of DLEs; response logic coupled to the plurality of DLEs, having first and second inputs and operative to produce strobe markers in response to timing markers received from the plurality of DLEs; and a loop-back circuit.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs) adapted to be connected in a loop; a state machine coupled to the plurality of DLEs and operative to provide state data for the plurality of DLEs; a start oscillation signal receiving circuit coupled to the loop and operative to trigger the loop in response to receipt of a start oscillation signal; and a calibration circuit coupled to the loop and operative to acquire calibration data for the plurality of DLEs.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.