Patents by Inventor Ahmed T. Sayed Gamal El Din
Ahmed T. Sayed Gamal El Din has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9459918Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: GrantFiled: January 30, 2014Date of Patent: October 4, 2016Assignee: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Publication number: 20140149990Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali A. EL-MOURSY, Hisham E. ELSHISHINY, Ahmed T. SAYED GAMAL EL DIN
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Patent number: 8677361Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: GrantFiled: September 28, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Patent number: 8656408Abstract: Guiding OS thread scheduling in multi-core and/or multi-threaded microprocessors by: determining, for each thread among the active threads, the power consumed by each instruction type associated with an instruction executed by the thread during the last context switch interval; determining for each thread among the active threads, the power consumption expected for each instruction type associated with an instruction scheduled by said thread during the next context switch interval; generating at least one combination of N threads among the active threads (M), and for each generated combination determining if the combination of N threads satisfies a main condition related to the power consumption per instruction type expected for each thread of the thread combination during the next context switch interval and to the thread power consumption per instruction type determined for each thread of the thread combination during the last context switch interval; and selecting a combination of N threads.Type: GrantFiled: September 28, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationsInventors: Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Publication number: 20120192195Abstract: Scheduling threads in a multi-threaded/multi-core processor having a given instruction window, and scheduling a predefined number N of threads among a set of M active threads in each context switch interval are provided. The actual power consumption of each running thread during a given context switch interval is determined, and a predefined priority level is associated with each thread among the active threads based on the actual power consumption determined for the threads. The power consumption expected for each active thread during the next context switch interval in the current instruction window (CIW_Power_Th) is predicted, and a set of threads to be scheduled among the active threads are selected from the priority level associated with each active thread and the power consumption predicted for each active thread in the current instruction window.Type: ApplicationFiled: September 28, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Ali A. El-Moursy, Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din
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Publication number: 20120084790Abstract: Guiding OS thread scheduling in multi-core and/or multi-threaded microprocessors by: determining, for each thread among the active threads, the power consumed by each instruction type associated with an instruction executed by the thread during the last context switch interval; determining for each thread among the active threads, the power consumption expected for each instruction type associated with an instruction scheduled by said thread during the next context switch interval; generating at least one combination of N threads among the active threads (M), and for each generated combination determining if the combination of N threads satisfies a main condition related to the power consumption per instruction type expected for each thread of the thread combination during the next context switch interval and to the thread power consumption per instruction type determined for each thread of the thread combination during the last context switch interval; and selecting a combination of N threads.Type: ApplicationFiled: September 28, 2011Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hisham E. Elshishiny, Ahmed T. Sayed Gamal El Din