Abstract: A package comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a plurality of post interconnects. The plurality of post interconnects include a post interconnect comprising a profile cross section that includes a trapezoid shape.

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability.

Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Abstract: A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer and a redistribution interconnect comprising a first surface and a second surface opposite to the first surface. The redistribution interconnect is formed over the passivation layer such that the first surface is over the passivation layer and the second surface is free of contact with any passivation layer. The device includes a bump interconnect coupled to the second surface of the redistribution interconnect. In some implementations, the bump interconnect comprises a surface that faces the redistribution interconnect, and wherein an entire surface of the bump interconnect that faces the redistribution interconnect is free of contact with the passivation layer.

Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Abstract: A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.

Abstract: A novel die seal design, and method for utilization thereof, controls contact of a mold material with the surfaces of a semiconductor die during application, reducing stresses due to a mismatch of the coefficient of thermal expansion of the mold material and the semiconductor die, thereby reducing cracking of the semiconductor die, resulting in increased yields and lower costs, and permits reuse of elements of a mold tool over a range of die sizes.

Abstract: A semiconductor package which is structured to allow for the edge mounting thereof in a vertical mount orientation. The semiconductor package comprises a flexible substrate or “flex circuit.” The flexible substrate includes a conductive pattern disposed on a first surface thereof, and a plurality of conductive pads or terminals disposed on a second surface thereof which is disposed in opposed relation to the first surface. Mounted to the first surface of the flexible substrate are one or more electronic components such as semiconductor dies. The semiconductor die(s) is/are electrically connected to the conductive pattern, and thereafter covered or encapsulated by a package body applied to a portion of the first surface of the flexible substrate. That portion of the flexible substrate including the conductive pads or terminals formed on the second surface thereof is thereafter folded and adhered to a portion of the package body through the use of a suitable adhesive.

Abstract: A lead frame comprising a frame which defines a central opening. Disposed within the central opening is a die pad which is connected to the frame. Also connected to the frame are a plurality of leads which extend within the opening toward the die pad. Each of the leads defines opposed top and bottom surfaces, an inner end, an outer end, and an opposed pair of side surfaces. The bottom surface and the outer end collectively define a corner region of the lead. Formed within the corner region is a recess which is sized and configured to accommodate the flow of reflow solder thereinto.

Abstract: A lead frame strip for use in the manufacture of integrated circuit chip packages. The strip comprises at least one array defining a multiplicity of lead frames. The lead frames each include an outer frame defining a central opening having a die pad disposed therein. Attached to the outer frame and extending toward the die pad in spaced relation to each other are a plurality of leads. The outer frames are integrally connected to each other such that the lead frames are arranged in a matrix wherein the leads thereof extend in multiple rows and columns. The leads of the lead frames within each of the rows and columns are arranged in sets which are disposed in spaced relation to each other. A plurality of openings are formed within the strip between and in alignment with the leads of each of the lead frames within each of the rows and columns.

Abstract: A lead frame comprising a frame which defines a central opening. Disposed within the central opening is a die pad which is connected to the frame. Also connected to the frame are a plurality of leads which extend within the opening toward the die pad. Each of the leads defines opposed top and bottom surfaces, an inner end, an outer end, and an opposed pair of side surfaces. The bottom surface and the outer end collectively define a corner region of the lead. Formed within the corner region is a recess which is sized and configured to accommodate the flow of reflow solder thereinto.