Abstract: Methods, systems, and devices are described for a power-on sequence for a circuit. A sequence generator for an electronic system may control various power domains to enter known states and prevent unwanted states as other domains of the system power-up. Regulator modules may be controlled to remain in an inoperable state until a reference voltage stabilizes at a predetermined reference level. The regulator modules regulate a received voltage supply to output a regulated voltage at the reference level, the regulated voltage set via a comparison to the reference voltage. Various analog and digital modules may be controlled to remain in an known state until the regulated voltage stabilizes at substantially the reference level. Additional sequencing is described for other dependencies, as well.

Abstract: A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once.

Abstract: An apparatus and a method to initiate spread spectrum modulation have been presented. In one embodiment, a spread spectrum off to spread spectrum on transition circuit is used to start spread spectrum modulation. The spread spectrum off to spread spectrum on transition circuit may include a phase lock loop (PLL) to output a clock signal. The spread spectrum off to spread spectrum on transition circuit may further include a control block coupled to the PLL to cause the PLL to lock the clock signal to a predetermined center frequency before transitioning from a non-spread spectrum mode into a spread spectrum mode.

Abstract: A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier.

Abstract: A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier.

Abstract: Methods, systems, and devices are described for a power-on sequence for a circuit. A sequence generator for an electronic system may control various power domains to enter known states and prevent unwanted states as other domains of the system power-up. Regulator modules may be controlled to remain in an inoperable state until a reference voltage stabilizes at a predetermined reference level. The regulator modules regulate a received voltage supply to output a regulated voltage at the reference level, the regulated voltage set via a comparison to the reference voltage. Various analog and digital modules may be controlled to remain in an known state until the regulated voltage stabilizes at substantially the reference level. Additional sequencing is described for other dependencies, as well.

Abstract: A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once.

Abstract: Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

Abstract: Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single end seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.