Abstract: Disclosed herein is a system and method for using reconfigurable logic for hardware redaction in which the critical IP is obfuscated by replacing it with an eFPGA, thereby entirely concealing the logic and interconnects from reverse engineers and untrusted fabrication facilities. The non-critical intellectual property of the hardware is left unaltered such that the overall VLSI overheads (e.g., area, power, and performance) can be kept to a minimum.

Abstract: Disclosed herein is a method for performing top-down design for optimizing synthesizable FPGA fabrics which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. This is accomplished by providing the EDA tools with a global timing view spanning multiple tiles. The method restructures the switch-box muliplexers in a unique way to enable the use of powerful static timing analysis (STA) exceptions supported by modern EDA tools to work around the problem of combinational loops and long false paths created by the interconnect mesh in the FPGA fabric.

Abstract: Disclosed herein is a platform comprising a hardware compiler framework to directly instrument an RTL representation of an input design with a fault injection processor enabling the execution of arbitrary error injection requests from the user and communication with the design under test to target specific design sections for fault injection.