Abstract: A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.

Abstract: An N-channel and P-channel MOSFET include counterdoping of a threshold voltage (V.sub.T) ion implant for reducing substrate sensitivity and source/drain junction capacitance. An arsenic (As) compensated boron (B) implant is provided in the N-channel MOSFET. A boron (B) compensated arsenic (As) implant is provided in the P-channel MOSFET.

Abstract: A method of forming a SOI integrated circuit includes defining thin silicon mesas by etching a device layer down to the underlying insulator, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature PECVD process, with nitride sidewalls on the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000.ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.

Abstract: A method of forming a SOI integrated circuit includes defining thin silicon mesas by wet etching a device layer having the <100> orientation down to the underlying insulator so that the (111) crystal planes control the lateral etching, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature CVD process, with nitride sidewalls on the (111) planes of the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000 .ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.