Abstract: Disclosed are apparatuses and methods with crypto processing. Computing devices may be interconnected to each other. Each computing device may be configured to perform polynomial operations based on homomorphic encryption. Memories may be configured to store instructions. Controllers may be configured to transfer instructions from the memories to the computing devices. One or more of the computing devices may each be configured to individually process, in parallel, at least a portion of the polynomial operations based on the homomorphic encryption according to an instruction transferred from a corresponding memory.

Abstract: A processor-implemented method with a polynomial multiplication operation includes obtaining an auxiliary modulus corresponding to moduli according to a Chinese remainder theorem (CRT), performing a number theoretic transform (NTT) operation with respect to the auxiliary modulus on a result of a modulo operation of the moduli for each of a first polynomial and a second polynomial, performing an element-wise multiplication operation between an NTT operation result corresponding to the first polynomial and an NTT operation result corresponding to the second polynomial, and transforming a result of the element-wise multiplication operation into a polynomial corresponding to each of the moduli.

Abstract: An electronic device includes a substrate, an interposer attached to a top of the substrate and comprising a plurality of through-silicon vias (TSVs), a plurality of core chiplets attached to a top of the interposer, and a plurality of memory chiplets attached to the top of the interposer, wherein each of the plurality of core chiplets comprises a number-theoretic transform (NTT) module.

Abstract: An operation method includes obtaining an input matrix including a coefficient of a polynomial, based on a preprocessing unit (PU), performing a preprocessing operation on the coefficient, based on a first number-theoretic transform (NTT) architecture, performing a first NTT operation on a column element of the input matrix for which the preprocessing operation is completed, performing a Hadamard product operation between a result of the first NTT operation and a twiddle factor, and based on a second NTT architecture, performing a second NTT operation on a row element of the input matrix for which the Hadamard product operation is completed.

Abstract: An apparatus includes: one or more memories configured to store an operation key comprising a re-linearization key and ciphertext comprising a plurality of modules; a controller configured to schedule a homomorphic encryption operation based on the ciphertext, based on at least one of the plurality of modules and a modulus of the ciphertext; and a plurality of operation devices configured to parallelly process respective parts of the homomorphic encryption operation according to a result of the scheduling.

Abstract: An apparatus and method with homomorphic encryption are included. An apparatus includes a processor configured to, and/or coupled with a memory storing instructions to configure the processor to: generate, from a ciphertext corresponding to a polynomial having a first degree for performing a homomorphic encryption operation, split polynomials having a second degree by factorizing the polynomial, wherein the split polynomials have a second degree that is less than the first degree, generate partial operation results by performing an element-wise operation using the split polynomials, and generate a homomorphic encryption operation result corresponding to the ciphertext by joining the partial operation results.

Abstract: Disclosed are apparatuses and methods with crypto processing. Computing devices may be interconnected to each other. Each computing device may be configured to perform polynomial operations based on homomorphic encryption. Memories may be configured to store instructions. Controllers may be configured to transfer instructions from the memories to the computing devices. One or more of the computing devices may each be configured to individually process, in parallel, at least a portion of the polynomial operations based on the homomorphic encryption according to an instruction transferred from a corresponding memory.