Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: In a class of embodiments, a method and apparatus for detecting freefall of a disk device (thereby predicting that the disk device will likely suffer imminent physical impact) and typically also preventing damage that a disk drive of the device would otherwise suffer if and when a predicted impact occurs. In some embodiments, a disk device includes a freefall detection processor and a CPU. The freefall detection processor is configured to monitor acceleration data to determine whether the disk device is in freefall and to perform at least one other operation (e.g., decoding of MP3-encoded audio data to generate decoded audio data) while the CPU performs at least one other task. Other embodiments pertain to a portable device including a digital audio processing subsystem and an accelerometer.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.

Abstract: A dual rate echo canceller for simultaneous support of multiple annexes is provided. The present invention provides an efficient Reduced Complexity Dual Rate Echo Chancellor (RCDR-EC) architecture for ADSL CPE for simultaneous support of a plurality of annexes, such as Annex A and Annex B of G.992.1. In addition, low complexity LMS update rules are proposed for adaptive training RCDR-EC. In addition, RCDR-EC of the present invention may operate at the transmit rate, the lower of the two rates, thereby requiring less computation per data sample. The present invention provides an echo canceller structure for full rate ADSL CPE. Another aspect of the present invention is directed to designing the echo canceller flexible enough to simultaneously support, at least, Annex A and Annex B of G.992.1. Another aspect of the present invention is further directed to obtaining an efficient rate matching echo canceller implementation for full rate ADSL CPE as well as other applications.