Abstract: Disclosed herein is a novel system and method for detecting, localizing, and correcting configuration upsets of an SRAM-based FPGA design caused by radiation exposure. The radiation-hardened FPGA uses embedded strike sensors distributed throughout the FPGA fabric, coupled with an error handler to correct the upsets using a redundant on-chip copy of the configuration.

Abstract: Disclosed herein is a method for performing top-down design for optimizing synthesizable FPGA fabrics which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. This is accomplished by providing the EDA tools with a global timing view spanning multiple tiles. The method restructures the switch-box muliplexers in a unique way to enable the use of powerful static timing analysis (STA) exceptions supported by modern EDA tools to work around the problem of combinational loops and long false paths created by the interconnect mesh in the FPGA fabric.