Abstract: A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N×M×Z topology, the nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N×M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Abstract: According to embodiments of the present disclosure, methods of and computer program products for operating a plurality of classifiers are provided. A plurality of input entities are read, each input entity having an associated target label. The input entities are provided to a first classifier, and a category of each input entity is obtained therefrom. A feature map is determined for each input entity. Each feature map is provided to each of a set of classifiers, and an assigned label is obtained for each feature map from each of the set of classifiers. Each classifier is associated with one of the categories. For each classifier, the assigned label for each feature map is compared to the target labels to determine a plurality of gradients. The plurality of gradients are masked according to each category, yielding a masked set of gradients for each category. Each classifier is trained according its associated masked gradients.

Abstract: An imaging system is provided. A first imaging system captures initial sensor data in a form of visible domain data. A second imaging system captures subsequent sensor data in a form of second domain data, wherein the initial and subsequent sensor data are of different spectral domains. A controller subsystem detects at least one region of interest in real-time by applying a machine learning technique to the visible domain data, localizes at least one object of interest in the at least one region of interest to generate positional data for the at least one object of interest, and autonomously steers a point of focus of the second imaging system to a region of a scene including the object of interest to capture the second domain data responsive to the positional data.

Abstract: A system according to one embodiment includes a collection of computing nodes arranged in a mesh of N×M×Z topology, the nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4; a collection of I/O connections interfaced with one of the sides of the mesh, said side having N×M nodes, each of the I/O connections being tied to a unique one of the nodes in said side; and I/O cards that are tied to the I/O connections.

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Abstract: A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N×M×Z topology, the computing nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N?×M?×Z? topology, wherein at least two of N, M, and Z values are different from their corresponding N?, M?, and Z? values, and wherein N×M×Z is equal to N?×M?×Z?; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

Abstract: According to embodiments of the present disclosure, methods of and computer program products for operating a plurality of classifiers are provided. A plurality of input entities are read, each input entity having an associated target label. The input entities are provided to a first classifier, and a category of each input entity is obtained therefrom. A feature map is determined for each input entity. Each feature map is provided to each of a set of classifiers, and an assigned label is obtained for each feature map from each of the set of classifiers. Each classifier is associated with one of the categories. For each classifier, the assigned label for each feature map is compared to the target labels to determine a plurality of gradients. The plurality of gradients are masked according to each category, yielding a masked set of gradients for each category. Each classifier is trained according its associated masked gradients.

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Abstract: A computer-implemented method is provided for use with a reconfigurable computational device having a collection of computing nodes arranged in a mesh of N× M×Z topology, the computing nodes including computational hardware, wherein Z<N and Z<M, and wherein N and M are at least equal to 4. The method includes using the computational device to perform computations characterized by (i) an initial system I/O bandwidth and (ii) an initial system node-to-node latency; reconfiguring the device into a mesh of N?×M?×Z? topology, wherein at least two of N, M, and Z values are different from their corresponding N?, M?, and Z? values, and wherein N×M×Z is equal to N?×M?×Z?; and using the device to perform computations characterized by (i) a modified system I/O bandwidth and (ii) a modified system node-to-node latency.

Abstract: A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

Abstract: Memory-augmented neural networks are provided. In various embodiments, an encoder artificial neural network is adapted to receive an input and provide an encoded output based on the input. A plurality of decoder artificial neural networks is provided, each adapted to receive an encoded input and provide an output based on the encoded input. A memory is operatively coupled to the encoder artificial neural network and to the plurality of decoder artificial neural networks. The memory is adapted to store the encoded output of the encoder artificial neural network and provide the encoded input to the plurality of decoder artificial neural networks.

Abstract: A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.

Abstract: A field-effect transistor (FET) and method of manufacture thereof include a gate, a doped semiconductor structure formed on top of the planar source and drain regions, and a sheath of conducting materials flanking the formed doped semiconductor structure, where the sheath is perpendicular to a surface of the planar source and drain regions.

Abstract: A field-effect transistor (FET) and method of manufacture thereof include a gate, a pillar of grown on a top of the planar source and drain regions, and a conductive sheath flanking the pillar, the sheath is bent up, alongside, and over the gate.

Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.

Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

Abstract: A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.