Abstract: Disclosed are an electrolyte membrane of a membrane-electrode assembly including an electronic insulation layer, which greatly improves the durability of the electrolyte membrane, and a method of preparing the same. The electrolyte membrane includes an ion exchange layer and an electronic insulation layer provided on the ion exchange layer, and the electronic insulation layer includes one or more catalyst complexes, and a second ionomer Particularly, each of the one or more catalyst complex includes a catalyst particle and a first ionomer coated on the entirety or a portion of the surface of the catalyst particle, and the one or more catalyst complexes are dispersed the second ionomer.

Abstract: A display device includes a sensor having a detection electrode. An optical pattern layer is disposed directly on the sensor and includes a plurality of transmission portions and a light blocking portion. A display panel is disposed on the optical pattern layer. A minimum distance between the detection electrode and the light blocking portion is in a range of 1 micrometer-5 micrometers.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die.

Abstract: A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die.

Abstract: A plurality of fuse cells includes a first fuse cell and a second fuse cell. Each of the first and second fuse cells includes a first anti-fuse and a second anti-fuse. A method of programming the fuse cells includes rupturing the first anti-fuse of the first fuse cell based on first data loaded to a program control circuit. The method includes rupturing the second anti-fuse of the first fuse cell before loading second data to the program control circuit. The second data is for rupturing the first anti-fuse of the second fuse cell or the second anti-fuse of the second fuse cell.

Abstract: A process for increasing the production of light olefin hydrocarbons from a hydrocarbon feedstock. A process for producing an aromatic hydrocarbon mixture and liquefied petroleum gas (LPG) from a hydrocarbon mixture, and a process for producing a hydrocarbon feedstock which is capable of being used as a feedstock in the former process, that is to say, a fluidized catalytic cracking (FCC) process, a catalytic reforming process, and/or a pyrolysis process, are integrated, thereby it is possible to increase the production of C2-C4 light olefin hydrocarbons.

Abstract: A porous solid acid catalyst for producing light olefins is prepared through pillaring and a solid state reaction of a raw material mixture. The catalyst is made of a porous material having a crystalline structure that is different from that of the raw material mixture. The catalyst exhibits excellent catalytic activity (i.e., conversion and selectivity) in the production of light olefins from hydrocarbon feeds such as full range naphthas.

Abstract: A method for implementing an Electronic Program Guide (EPG) A method for implementing a digital Electronic Program guide (EPG) includes the steps of: displaying a date/time selection image including a plurality of cells; and providing a user with an EPG associated with a date and time corresponding to a specific cell if the user designates the specific cell contained in the date/time selection image. The method allows the user to select EPG information corresponding to desired date and time using an additional window, such that the user can directly recognize EPG information associated with a desired date and time zone, and can conveniently search for the EPG information.