Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Abstract: A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

Abstract: Provided are improved nozzles suitable for injecting source gases or other gases into a plasma chamber in which the gas is conveyed along a single passage or channel to an outlet region at which point the single channel is divided into a plurality of outlet channels. The outlet channels are configured to suppress formation of a plasma within the nozzle itself, thereby reducing deposition and/or damage within the nozzle. The outlet channels may be defined through the use of one or more insertion members that can be inserted in the outlet region of the nozzle and may be used in combination with an outer pipe attached to a supply pipe for completing the nozzle assembly.

Abstract: Provided is a high density plasma chemical vapor deposition (HDP-CVD) apparatus that includes a plurality of nozzles and/or injection pipes arranged for injecting a source gas mixture into a reaction chamber. The nozzles will each include an outlet region that includes a plurality of outlet channels or ports, the outlet channels are, in turn, configured to have a sufficiently small width and a sufficient length to suppress the formation of a plasma within the source gases passing through the respective nozzles. By suppressing the formation of a plasma within the nozzles, the thickness of deposits formed on the nozzles during the deposition processes can be maintained at a level generally no greater than deposits formed on the other chamber surfaces. This control of the deposit thickness allows the nozzles to be cleaned effectively by the same cleaning process applied to the chamber.