Patents by Inventor Ahsanur Rahman
Ahsanur Rahman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240136003Abstract: A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.Type: ApplicationFiled: December 23, 2023Publication date: April 25, 2024Inventors: Tarek Ahmed AMEEN BESHARI, Shantanu R. RAJWADE, Ahsanur RAHMAN, Sagar UPADHYAY, Pratyush CHANDRAPATI
-
Publication number: 20230082368Abstract: Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Chang Wan Ha, Binh Ngo, Ahsanur Rahman, Radhika Chinnammagari, Sagar Upadhyay
-
Publication number: 20220415380Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Naveen Prabhu Vittal Prabhu, Aliasgar S. Madraswala, Bharat Pathak, Binh Ngo, Netra Mahuli, Ahsanur Rahman
-
Publication number: 20220399057Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 9, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Chang Wan Ha, Deepak Thimmegowda, Hoon Koh, Richard M. Gularte, Liu Liu, David Meyaard, Ahsanur Rahman
-
Publication number: 20220172784Abstract: A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.Type: ApplicationFiled: November 30, 2020Publication date: June 2, 2022Inventors: Shantanu R. RAJWADE, Bayan NASRI, Tzu-Ning FANG, Rezaul HAQUE, Dhanashree R. KULKARNI, Narayanan RAMANAN, Matin AMANI, Ahsanur RAHMAN, Seong Je PARK, Netra MAHULI
-
Patent number: 7551489Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.Type: GrantFiled: December 28, 2005Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Kerry D. Tedrow, Dung Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad P. Monasa, Matthew Goldman
-
Patent number: 7525840Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: GrantFiled: August 7, 2007Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Ahsanur Rahman, Rezaul Haque, Kerry D. Tedrow
-
Publication number: 20070268758Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: ApplicationFiled: August 7, 2007Publication date: November 22, 2007Applicant: INTEL CORPORATIONInventors: Ahsanur Rahman, Rezaul Haque, Kerry Tedrow
-
Patent number: 7272041Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: GrantFiled: June 30, 2005Date of Patent: September 18, 2007Assignee: Intel CorporationInventors: Ahsanur Rahman, Rezaul Haque, Kerry D. Tedrow
-
Publication number: 20070171708Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.Type: ApplicationFiled: December 28, 2005Publication date: July 26, 2007Inventors: Kerry Tedrow, Dung Nguyen, Bo Li, Rezaul Haque, Ahsanur Rahman, Saad Monasa, Matthew Goldman
-
Publication number: 20070002613Abstract: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: INTEL CORPORATIONInventors: Ahsanur Rahman, Rezaul Haque, Kerry Tedrow