Abstract: In one embodiment, a semiconductor device includes a stacked film including a plurality of first insulators and a plurality of electrode layers that are alternately stacked in a first direction. The device includes a first plug provided on a first electrode layer among the plurality of electrode layers, and having a tube shape extending in the first direction. The device includes a second insulator provided in the first plug and the first electrode layer, and having a columnar shape extending in the first direction. Furthermore, a diameter of a side face of the first plug enclosing the second insulator is larger than a diameter of a side face of the first electrode layer enclosing the second insulator.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a circuit portion, a stacked body, at least one columnar member, a device isolation portion, and at least one first support member. The columnar member is in contact with an interconnect layer, and includes a contact extending in a stacking direction of a plurality of electrode films in the stacked body. The device isolation portion is provided in the stacked body and extends in a first direction and the stacking direction. The first support member is provided in the stacked body, extends in the stacking direction, and is located on the device isolation portion in a second direction crossing the first direction and along the upper surface of the substrate.

Abstract: A simulation device of a semiconductor device according to an embodiment is a simulation device for analyzing a structural defect of the semiconductor device, the semiconductor device having wiring lines disposed three-dimensionally therein, and the simulation device of the semiconductor device comprises: a correct structure acquiring unit that acquires a correct structure of the semiconductor device; a comparative structure acquiring unit that acquires a comparative structure, the comparative structure being a structure of the semiconductor device manufactured under a certain condition; a difference extracting unit that extracts a difference of the comparative structure with respect to the correct structure; and a defect determining unit that determines a defect of the comparative structure from the difference, the defect determining unit including an open/short attribute determining unit that determines whether the difference is an open attribute positioned inside the correct structure or a short attribute

Abstract: In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations.

Abstract: In accordance with an embodiment, a design method includes classifying interconnection line patterns each including a space between interconnection lines among design layout patterns of a semiconductor element with an air gap between the interconnection lines, on the basis of characteristics of the space, acquiring a basic amount of the classified interconnection line pattern, predicting a position where each air gap is highest and a height of the position for each classified interconnection line pattern, and suitably adjusting the arrangement of the interconnection lines in the design layout pattern in accordance with the predicted position and height. The basic amount is acquired from a shape of the classified interconnection line pattern. The position where each air gap is highest and the height of the position are predicted by collating data of a correlation between the width of the space and the height of the air gap with the basic amount.

Abstract: In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations.