Patents by Inventor Aidan Murphy
Aidan Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12644906Abstract: A fence tester for testing the voltage in an electric fence comprises a handle member and a blade member pivotally coupled to the handle member between an open state extending from the handle member and a closed state partly recessed into the handle member. The handle member defines a hollow interior region, and comprises a printed circuit board having an electronic monitoring circuit therein. An antenna coupled to the electronic monitoring circuit is configured to conduct an electrical current induced therein by an electric field generated by a pulsating voltage in the electric fence when the fence tester is located adjacent the electric fence. A latching element located in the handle member operated by a manually operated operating element in the handle member latches the blade member in the open state and the closed state.Type: GrantFiled: October 5, 2023Date of Patent: June 2, 2026Assignee: FORCEFIELD ACTIVE TECHNOLOGY LIMITEDInventor: Aidan Murphy
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Publication number: 20240118312Abstract: A fence tester for testing the voltage in an electric fence comprises a handle member and a blade member pivotally coupled to the handle member between an open state extending from the handle member and a closed state partly recessed into the handle member. The handle member defines a hollow interior region, and comprises a printed circuit board having an electronic monitoring circuit therein. An antenna coupled to the electronic monitoring circuit is configured to conduct an electrical current induced therein by an electric field generated by a pulsating voltage in the electric fence when the fence tester is located adjacent the electric fence. A latching element located in the handle member operated by a manually operated operating element in the handle member latches the blade member in the open state and the closed state.Type: ApplicationFiled: October 5, 2023Publication date: April 11, 2024Applicant: Forcefield Active Technology LimitedInventor: Aidan MURPHY
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Patent number: 9437121Abstract: A holder (100) for a folded card (102), the folded card (102) being of the type having a spine (108) and at least two sheets (110). The holder (100) having a holder support (104) for engagement with a surface for preventing the holder (100) being disturbed in an outdoor environment and a card supporting arrangement (106) mounted on the holder support (104). The card supporting arrangement (104) having an assembly for supporting the spine (108) of the folded card (102) and for engaging at least a portion of the sheets (110) of the folded card (102) on opposing sides of the spine (108) holding the folded card (102) open at a pre-determined angle.Type: GrantFiled: February 8, 2012Date of Patent: September 6, 2016Inventor: Aidan Murphy
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Patent number: 8630593Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.Type: GrantFiled: August 26, 2008Date of Patent: January 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Norman Beamish, Niall Kearney, Aidan Murphy
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Publication number: 20130313397Abstract: A holder (100) for a folded card (102), the folded card (102) being of the type having a spine (108) and at least two sheets (110). The holder (100) having a holder support (104) for engagement with a surface for preventing the holder (100) being disturbed in an outdoor environment and a card supporting arrangement (106) mounted on the holder support (104). The card supporting arrangement (104) having an assembly for supporting the spine (108) of the folded card (102) and for engaging at least a portion of the sheets (110) of the folded card (102) on opposing sides of the spine (108) holding the folded card (102) open at a pre-determined angle.Type: ApplicationFiled: February 8, 2012Publication date: November 28, 2013Inventor: Aidan Murphy
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Patent number: 8310362Abstract: A method of processing location information on a mobile device which includes a primary receiver for receiving a primary signal; a diversity receiver for receiving a diversity signal or location information; a diversity combiner which can combine primary and diversity signals to form a combined signal; and a first processing unit for processing the combined signal; the method comprising the steps of: identifying whether the device is in a location mode or a diversity mode; if the device is in location mode, disabling the diversity combiner; passing the output from the primary receiver directly to the first processing unit; and passing location information from the diversity receiver to a location processing unit.Type: GrantFiled: March 26, 2007Date of Patent: November 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Norman Beamish, Wayne Edwards, Aidan Murphy, Hugh O Brien, Conor O'Keeffe, Patrick Pratt, David Redmond, Daniel B Schwartz, Keith Tilley
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Publication number: 20110260761Abstract: An integrated circuit comprises a digital phase-locked loop for a wireless communications unit. The digital phase-locked loop comprises a voltage controlled oscillator and a digital tuning subsystem. An input of the digital tuning subsystem receives the output signal from the voltage controlled oscillator, and an output of the digital tuning subsystem is supplied to the voltage controlled oscillator. A digital voltage generator is adapted to store at least two predetermined forcing voltages. The digital voltage generator is adapted to select one of the at least two predetermined forcing voltages, in dependence on a current temperature value, and to supply it as a forcing voltage to an input of the voltage controlled oscillator, prior to the phase locked loop achieving lock. A wireless communication unit and a method of tuning a phase-locked loop are also provided.Type: ApplicationFiled: October 17, 2008Publication date: October 27, 2011Inventors: Niall Kearney, Aidan Murphy
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Publication number: 20110151804Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.Type: ApplicationFiled: August 26, 2008Publication date: June 23, 2011Applicant: Freescale Semiconductor ,Inc.Inventors: Norman Beamish, Niall Kearney, Aidan Murphy
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Publication number: 20100117824Abstract: A method of processing location information on a mobile device which includes a primary receiver for receiving a primary signal; a diversity receiver for receiving a diversity signal or location information; a diversity combiner which can combine primary and diversity signals to form a combined signal; and a first processing unit for processing the combined signal; the method comprising the steps of: identifying whether the device is in a location mode or a diversity mode; if the device is in location mode, disabling the diversity combiner; passing the output from the primary receiver directly to the first processing unit; and passing location information from the diversity receiver to a location processing unit.Type: ApplicationFiled: March 26, 2007Publication date: May 13, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Norman Beamish, Wayne Edwrards, Aidan Murphy, Huge O Brien, Conor O'Keeffe, Patrick Pratt, David Redmond, Daniel B. Schwartz, Keith Tilley