Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.