Patents by Inventor Aidan Walsh

Aidan Walsh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100312306
    Abstract: This invention is a pair of Compression Tights that fit very snugly on the legs and stimulate the cells of the muscle via light, almost imperceptible, electric pulses. These tights can be worn during exercise to complement the benefits of exercise or after exercise to enhance the recovery process. Unlike current muscle stimulators, CEPT does not try to contract the muscle, instead it lightly stimulates the muscle. During use, an individual will notice a light tingle through the muscle. This device is not to be confused with stimulators designed to tone muscles, heal injuries, burn calories, or teach muscle memory.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Inventors: Aidan Walsh, Alexander Wechsler
  • Patent number: 6858510
    Abstract: A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: February 22, 2005
    Assignee: General Semiconductor, Inc.
    Inventors: Willem G. Einthoven, Anthony Ginty, Aidan Walsh
  • Publication number: 20030205775
    Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p−n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
    Type: Application
    Filed: April 24, 2003
    Publication date: November 6, 2003
    Inventors: Willem G. Einthoven, Anthony Ginty, Aidan Walsh
  • Patent number: 6600204
    Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 29, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Willem G. Einthoven, Anthony Ginty, Aidan Walsh
  • Publication number: 20030010995
    Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
    Type: Application
    Filed: July 11, 2001
    Publication date: January 16, 2003
    Inventors: Willem G. Einthoven, Anthony Ginty, Aidan Walsh