Patents by Inventor Aifeng GAO

Aifeng GAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shift register and method for driving the same, gate driving circuit and display device
    Patent number: 11107382
    Abstract: A shift register, a method for driving the same, a gate driving circuit and a display device are provided. The shift register includes an input sub-circuit, a pull-down control sub-circuit, an output sub-circuit and a reset sub-circuit. The pull-down control sub-circuit is connected to a first signal input terminal, a pull-up node, a pull-down node and a first power terminal, and is configured to supply a first voltage signal of the first power terminal to the pull-down node under the control of the first input signal and a potential of the pull-up node. The output sub-circuit is connected to the first node and a second clock signal terminal, and is configured to output a second clock signal of the second clock signal terminal to a first output terminal and a second output terminal under the control of the potential of the pull-up node.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: August 31, 2021
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ying Wang, Meng Li, Aifeng Gao, Hongmin Li
  • SHIFT REGISTER AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
    Publication number: 20210118347
    Abstract: A shift register, a method for driving the same, a gate driving circuit and a display device are provided. The shift register includes an input sub-circuit, a pull-down control sub-circuit, an output sub-circuit and a reset sub-circuit. The pull-down control sub-circuit is connected to a first signal input terminal, a pull-up node, a pull-down node and a first power terminal, and is configured to supply a first voltage signal of the first power terminal to the pull-down node under the control of the first input signal and a potential of the pull-up node. The output sub-circuit is connected to the first node and a second clock signal terminal, and is configured to output a second clock signal of the second clock signal terminal to a first output terminal and a second output terminal under the control of the potential of the pull-up node.
    Type: Application
    Filed: April 3, 2020
    Publication date: April 22, 2021
    Applicants: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ying WANG, Meng LI, Aifeng GAO, Hongmin LI