Abstract: An information processing apparatus, a memory control method, and a memory control device are disclosed, the information processing apparatus including nodes each having a main memory, a processor including a cache memory, and a system controller. The system controller of at least one of the nodes includes a holding unit that holds address information corresponding to primary data stored in the main memory of its local node, and not cached in any of the cache memories of other nodes. The system controller of the at least one node may include local and global snoop control units, as well as a virtual tag expansion (VTAGx) unit, to maintain cache coherency, and under certain conditions, a snoop operation may be skipped or omitted.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return address stack by, changing the designate entry to indicate a one-step shallower entry when a call instruction is predicted during the instruction fetching, changing the designate entry independently of a push or pop operation to indicate a one-step deeper entry when a return instruction is predicted during an instruction fetching, and changing the designate entry depending upon a push and a pop operation when a call and return instruction is completed, thereby keeping a position of the designate entry. The entry designation unit designates an entry as predicted return address of a subroutine when the fetched instruction hitsin a branch history and determined as a return instruction.

Abstract: A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.

Abstract: An instruction control method carries out an instruction in a processor to process instructions by out-of-order processing, using delay instructions for branching. The processor includes a storage unit, a branch predictor making branch predictions and a control unit which successively stores a plurality of delay instructions in the storage unit together with information indicating whether or not branch instructions corresponding to the delay instructions are predicted to branch by the branch predictor.

Abstract: The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.

Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history).

Abstract: An instruction execution apparatus comprising a register storing a copy of contents of a maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at a head among all entries in an instruction storage device after execution of the instructions, a completion condition determination section 44 for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section 44 for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in a commitment stack entry, or clock frequency, is increased.

Abstract: The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.

Abstract: In the out-of-order process of an instruction, the address mode information of a fetched branch instruction is automatically transferred from an instruction fetch pipeline to an instruction execution pipeline. If the branch instruction is accompanied by an address mode change, the address mode after change designated by the branch instruction is adopted as the address mode of a branch destination. If the branch instruction is not accompanied by an address mode change, the transferred address mode information is adopted as the address mode of the branch destination.

Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.

Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history).

Abstract: An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

Abstract: An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

Abstract: A register number of a link register, which is specified by an instruction equivalent to a subroutine call, is registered. The number of a branch destination register in a branch instruction which can possibly be an instruction equivalent to a subroutine return is compared with the registered register number. If they match, this branch instruction is identified as an instruction equivalent to a subroutine return.

Abstract: An information processing device contains a branch instruction execution control apparatus including a branch reservation station unit as a stack waiting for a process. The branch reservation station unit generates an entry storing a branch or data required to process the branch if an instruction is decoded, and it is determined that the instruction is a branch instruction or a process is required for a branch. With the configuration, in the information processing device for executing sequentially given instructions, a process of a sequence of instructions containing a branch instruction can be performed at a high speed to process the branch instruction in an order different from an order specified by a program.

Abstract: A control reservation station stores the control information of a micro program to control one or more flows of an instruction process and controls each flow using the control information. A data buffer stores data to be used to control each flow and outputs the data at an appropriate timing.

Abstract: An instruction processing apparatus using a microprogram instruction which implements re-reading operation. The instruction execution apparatus is provided with a queue stack, a unit halting requests for reading subsequent instructions at the instruction of a microprogram, and a unit releasing this halt. Further, by instruction the reading of the subsequent instructions using the microprogram control information, it becomes possible to simultaneously execute the microprogram and instruction re-reading processing. Because the Program Status Word Instruction Address (PSWIAR) of the load control (LCTL) plus the instruction length of the PSWIAR makes an instruction fetch address of the LCTL, the hardware of the instruction re-read address production circuit (which is a part of the instruction processing circuit) can be used.

Abstract: An instruction execution apparatus comprising a register 43 for storing a copy of contents of the maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at the head among all entries in an instruction storage device 42 after execution of the instructions, a completion condition determination section 44 for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section 45 for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in the CSE, or clock frequency, is increased.