Patents by Inventor Aiichiro Sakumoto

Aiichiro Sakumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6563483
    Abstract: The present invention provides a liquid crystal display apparatus capable of reducing waving and shadowing. The driving circuit portion in the liquid crystal display apparatus according to the present invention has a random number generating circuit 2, a display data RAM 3, a display data RAM address decoder 7, and a row driver 8. The random number generating circuit 2 generates random numbers for setting the scanning order of the row electrodes. The row address decoder 7 sets the scanning order on the row electrodes. The column driver 6 supplies the video data of all the column electrodes corresponding to the scanning row electrode. The scanning order of the scanning lines is set by the random numbers generated by the random number generating circuit 2. Because of this, the scanning order becomes random at each frame, and the shadowing depending to the video data is reduced. Furthermore, because the adjacent scanning lines are not continuously scanned, the waving does not arise.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Aiichiro Sakumoto
  • Patent number: 5239191
    Abstract: Upon the making of a die-sort testing for a predetermined IC pattern formed on each chip area, a plurality of sets of output pads selectively supplied with output signals are formed on the chip area and connected with a connection pattern on a dicing line area, and one testing pad is provided for the respective set of the pads. The IC patterns are tested by electrically contacting the testing pad with corresponding probe needle of probe card in a die-sort machine.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aiichiro Sakumoto, Michihiro Kawakami
  • Patent number: 5132614
    Abstract: A semiconductor device in which a semiconductor chip has a plurality of output terminals which are connected to a common node outside of the chip itself and are arranged into at least one group. A selection circuit disposed within the semiconductor selects one output terminal from among the output terminals in the group and allows data to be supplied only to the selected terminal. After testing, the output terminals are disconnected from one another to allow the chip to function properly.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: July 21, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aiichiro Sakumoto, Akira Masuko, Ken Yamamoto