Patents by Inventor Aik Teong Tan

Aik Teong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9570419
    Abstract: A semiconductor wafer and a plurality of semiconductor dies are provided. The wafer and the dies each include first electrically conductive terminals arranged on a main surface. The wafer is permanently attached to each of the semiconductor dies such that the first terminals are electrically connected to one another. At least one of the wafer and the semiconductor dies is thinned. The wafer is diced so as to form a plurality of chip-stacks, each of the chip-stacks comprising one of the semiconductor dies permanently attached to a diced wafer chip. At least one of the first terminals in the chip-stack is accessible by a second electrically conductive terminal arranged on a rear surface and electrically connected to the first terminal by an electrical connector that is internal to a semiconductor body of either the semiconductor die or the diced wafer chip of the chip-stack.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventor: Aik Teong Tan
  • Publication number: 20160218080
    Abstract: A semiconductor wafer and a plurality of semiconductor dies are provided. The wafer and the dies each include first electrically conductive terminals arranged on a main surface. The wafer is permanently attached to each of the semiconductor dies such that the first terminals are electrically connected to one another. At least one of the wafer and the semiconductor dies is thinned. The wafer is diced so as to form a plurality of chip-stacks, each of the chip-stacks comprising one of the semiconductor dies permanently attached to a diced wafer chip. At least one of the first terminals in the chip-stack is accessible by a second electrically conductive terminal arranged on a rear surface and electrically connected to the first terminal by an electrical connector that is internal to a semiconductor body of either the semiconductor die or the diced wafer chip of the chip-stack.
    Type: Application
    Filed: January 27, 2015
    Publication date: July 28, 2016
    Inventor: Aik Teong Tan